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MOTOROLA
3-10
MC68HC11KW1
CENTRAL PROCESSING UNIT
3
BHS (rel)
Branch if higher or same
C = 0
REL
24
rr
3
— — — — — — — —
— — — —
BITA (opr)
Bit(s) test A with memory
A M
A
A
A
A
A
IMM
DIR
EXT
IND, X
IND, Y
85
95
B5
A5
18 A5
ii
dd
hh ll
ff
ff
2
3
4
4
5
0 —
BITB (opr)
Bit(s) test B with memory
B M
B
B
B
B
B
IMM
DIR
EXT
IND, X
IND, Y
C5
D5
F5
E5
18 E5
ii
dd
hh ll
ff
ff
2
3
4
4
5
— — — —
0 —
BLE (rel)
Branch if
≤
zero
Branch if lower
Z + (N
⊕
V) = 1
C = 1
REL
2F
rr
3
— — — — — — — —
BLO (rel)
REL
25
rr
3
— — — — — — — —
BLS (rel)
Branch if lower or same
C + Z = 1
N
⊕
V = 1
N = 1
REL
23
rr
3
— — — — — — — —
BLT (rel)
Branch if < zero
REL
2D
rr
3
— — — — — — — —
BMI (rel)
Branch if mnus
Branch if
≠
zero
Branch if plus
REL
2B
rr
3
— — — — — — — —
BNE (rel)
Z = 0
REL
26
rr
3
— — — — — — — —
BPL(rel)
N = 0
REL
2A
rr
3
— — — — — — — —
BRA (rel)
Branch always
1 = 1
REL
20
rr
3
— — — — — — — —
BRCLR(opr)
(msk)
(rel)
Branch if bit(s) clear
M mm= 0
DIR
IND, X
IND, Y
13
1F
18 1F
dd mmrr
ff mmrr
ff mmrr
6
7
8
— — — — — — — —
BRN (rel)
Branch never
1 = 0
REL
21
rr
3
— — — — — — — —
BRSET(opr)
(msk)
(rel)
Branch if bit(s) set
M mm= 0
DIR
IND, X
IND, Y
12
1E
18 1E
dd mmrr
ff mmrr
ff mmrr
6
7
8
— — — — — — — —
BSET (opr)
(msk)
Set bit(s)
M + mm
M
DIR
IND, X
IND, Y
14
1C
18 1C
dd mm
ff
ff
mm
mm
6
7
8
— — — —
0 —
BSR (rel)
Branch to subroutine
see Figure 3-2
REL
8D
rr
6
— — — — — — — —
BVC (rel)
Branch if overflow clear
V = 0
REL
28
rr
3
— — — — — — — —
BVS (rel)
Branch if overflow set
V = 1
REL
29
rr
3
— — — — — — — —
— — — —
— — — — — — — 0
CBA
Compare A with B
A – B
0
C
0
I
0
M
INH
11
—
2
CLC
Clear carry bit
INH
0C
—
2
CLI
Clear interrupt mask
INH
0E
—
2
— — — 0 — — — —
CLR (opr)
Clear memory byte
DIR
IND, X
IND, Y
7F
6F
18 6F
hh ll
ff
ff
6
6
7
— — — — 0 1 0 0
CLRA
Clear accumulator A
0
A
0
B
0
V
A – M
A
INH
4F
—
2
— — — — 0 1 0 0
CLRB
Clear accumulator B
B
INH
5F
—
2
— — — — 0 1 0 0
CLV
Clear overflow flag
INH
0A
—
2
— — — — — — 0 —
— — — —
CMPA (opr)
Compare A with memory
A
A
A
A
A
IMM
DIR
EXT
IND, X
IND, Y
81
91
B1
A1
18 A1
ii
dd
hh ll
ff
ff
2
3
4
4
5
CMPB (opr)
Compare B with memory
B – M
B
B
B
B
B
IMM
DIR
EXT
IND, X
IND, Y
C1
D1
F1
E1
18 E1
ii
dd
hh ll
ff
ff
2
3
4
4
5
— — — —
COM (opr)
Ones complement memory byte
$FF – M
M
EXT
IND, X
IND, Y
73
63
18 63
hh ll
ff
ff
6
6
7
— — — —
0 1
COMA
Ones complement A
$FF – A
A
$FF – B
B
A
INH
43
—
2
— — — —
— — — —
0 1
COMB
Ones complement B
B
INH
53
—
2
0 1
Table 3-2
Instruction set (Page 2 of 6)
Mnemonic
Operation
Description
Addressing
mode
Instruction
Condition codes
Opcode
Operand
Cycles
S X H
I N Z V C
TPG
38