
MC68HC11KW1
MOTOROLA
ix
INDEX
PORTF — Port F data reg.
6-7
PORTG — Port G data reg.
6-8
PORTH — Port H data reg.
6-10
PORTJ — Port J data reg.
6-11
PORTK — Port K data reg.
6-12
ports
A (Timer 1)
2-6
,
6-2
B (ADDR[15:8])
2-8
,
6-3
C (DATA[7:0])
2-8
,
6-4
D (SCI, SPI)
2-8
,
6-5
DDRA — Data direction reg. for port A
6-2
DDRB — Data direction reg. for port B
6-3
DDRC — Data direction reg. for port C
6-4
DDRD — Data direction reg. for port D
6-5
DDRF — Data direction reg. for port F
6-7
DDRG — Data direction reg. for port G
6-9
DDRH — Data direction reg. for port H
6-10
DDRJ — Data direction reg. for port J
6-11
DDRK — Data direction reg. for port K
6-12
E (A/D)
2-9
6-6
F (ADDR[7:0])
2-9
,
6-7
G (Memory expansion, A/D)
2-9
,
6-8
H (Chip select, PWM)
2-10
,
6-10
J (Timer 2)
2-10
6-11
K (Timer 3)
2-10
,
6-12
PGAR — Port G assignment register
4-32
PORTA — Port A data reg.
6-2
PORTB — Port B data reg.
6-3
PORTC — Port C data reg.
6-4
PORTD — Port D data reg.
6-5
PORTE — Port E data reg.
6-6
PORTF — Port F data reg.
6-7
PORTG — Port G data reg.
6-8
PORTH — Port H data reg.
6-10
PORTJ — Port J data reg.
6-11
PORTK — Port K data reg.
6-12
signals
2-6
power-on reset - see POR
PPAR — Port pull-up assignment reg.
6-13
PPOL[4:1] - bits in PWPOL
9-41
PPROG — EEPROM programming control reg.
4-41
PR[1:0] - bits in TMSK2
4-20
9-14
PR2A, PR2B - bits in TCTL4
9-21
PR3A, PR3B - bits in TCTL6
9-28
prebyte
3-7
prescaler, PWM
9-40
priorities, resets and interrupts
5-9
,
5-11
program chip select (CSPROG)
4-33
program counter (PC)
3-4
programming
CONFIG
4-44
EEPROM
4-41
protection
of memory
4-18
,
4-45
registers
4-10
PSEL[4:0] - bits in HPRIO
5-11
PT - bit in SCCR1
7-8
PTCON - bit in BPROT
4-19
pull-ups
6-13
pulse accumulator
9-1
,
9-33
block diagram
9-34
PACNT — Pulse accumulator count reg.
9-36
PACTL — Pulse accumulator control reg.
9-35
reset
5-8
TFLG2 — Timer interrupt flag 2 reg.
9-36
TMSK2 — Timer interrupt mask 2 reg.
9-36
pulse-width modulation - see PWM
PWCLK — PWM clock prescaler and 16-bit select reg.
9-38
PWCNT1–4 — PWM timer counter reg. 1 to 4
9-43
PWDTY1–4 — PWM timer duty cycle reg. 1 to 4
9-44
PWEN — PWM timer enable reg.
9-42
PWEN[4:1] - bits in PWEN
9-42
PWM
9-37
16-bit operation
9-38
block diagram
9-39
boundary conditions
9-44
clock select
9-40
duty cycle
9-37
,
9-44
periods
9-37
pins
9-37
PWCLK — PWM clock prescaler and 16-bit select reg.
9-38
PWCNT1–4 — PWM timer counter reg. 1 to 4
9-43
PWDTY1–4 — PWM timer duty cycle reg. 1 to 4
9-44
PWEN — PWM timer enable reg.
9-42
PWPER1–4 — PWM timer period reg. 1 to 4
9-43
PWPOL — PWM timer polarity & clock source select
reg.
9-41
PWSCAL — PWM timer prescaler reg.
9-41
PWPER1–4 — PWM timer period reg. 1 to 4
9-43
PWPOL — PWM timer polarity & clock source select reg.
9-41
PWSCAL — PWM timer prescaler reg.
9-41
R
R/T[7:0] - bits in SCDRL
7-12
R/W pin
2-6
R8 - bit in SCDRH
7-12
RAF - bit in SCSR2
7-11
RAM
4-4
data retention
4-4
security
4-45
RAM[3:0] - bit in INIT
4-13
RBOOT - bit in HPRIO
4-11
RDRF - bit in SCSR1
7-10
RE - bit in SCCR2
7-9
real-time interrupt - see RTI
receiver flags, SCI
7-13
REG[3:0] - bit in INIT
4-13
REL - relative addressing mode
3-8
RESET pin
2-2
resets
circuit
2-2
clock monitor
5-3
,
5-5
COP
5-2
5-3
effect on A/D
5-9
effect on COP
5-8
effect on CPU
5-7
TPG
231