參數(shù)資料
型號: MC68EN302CPV20BT
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù): 59/128頁
文件大小: 641K
代理商: MC68EN302CPV20BT
MC68EN302 DRAM Control Module
MOTOROLA
MC68EN302 REFERENCE MANUAL
3-5
Figure 3-2. Five-Clock Accesses with Three-Clock Precharge
3.7 REFRESH OPERATION
The MC68EN302 supports CAS before RAS refresh but note that refresh operation is not
synchronized to the bus activity. A special DRAMRW (Read/Write) pin is provided so that
refresh may occur regardless of the state of the processor bus. Only active bus cycles
operating in the DRAM banks will prevent a refresh cycle. Refresh occurs in both banks
simultaneously.
DRAM refresh is initiated during an idle state between bus cycles or during a bus cycle
which does not access the DRAM. If refresh is required concurrent with a DRAM access,
the MC68EN302 will perform the access while holding off the refresh. After the MC68EN302
initiates a refresh cycle, it must hold off DRAM accesses by inserting wait states until the
RAS precharge is complete following the refresh cycle.
Figure 3-3 shows a refresh cycle. In this case, there is a DRAM access waiting on the bus
and the DRAM access must wait until after RAS precharge.
S2 S3 S4 W
W
S1
CLOCK
S0
S5 S6 S7 S0 S1
ADDR
RAS
CAS
DRAMRW
DATA/
AS
UDS/LDS
S2 S3 S4 W
W
S5 S6 S7
WW
AMUX
PARITY
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