參數(shù)資料
型號： MC68EN302CPV20BT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù)： 101/128頁
文件大小： 641K
代理商： MC68EN302CPV20BT
Signal Descriptions
MOTOROLA
MC68EN302 REFERENCE MANUAL
5-7
5.4.1 AMUX - DRAM Address Mux
The AMUX pin is an output only pin provided for implementing external address muxing
circuitry when accessing DRAM. The user may require use of this signal if external masters
are utilizing the EN302 DRAM controller. When performing an access to the EN302 as a
slave, the address is driven as an input, preventing the EN302 DRAM controller from driving
the address bus. Because of this, external muxing must take place. The AMUX pin is also
useful in implementations where a linear DRAM space is required.
The AMUX signal appears on the pin if the PM0 bit of the MBCTRL = 0. If PM0 = 1 then the
pin becomes BRG1 instead.
5.4.2 RAS0 - DRAM Row Address Select, Bit Zero
When the PM1 bit of the MBCTRL = 0, this active low output signal is used to select one of
two banks of DRAM as determined by the DRAM Base Address Register 0 (DBA0).
If PM1 = 1 then the pin becomes BRG2/SDS2/PA7 and is bidirectional depending on the
function chosen
5.4.3 RAS1 - DRAM Row Address Select Bit 1
When the PM2 bit of the MBCTRL = 0, this active low output signal is used to select one of
two banks of DRAM as determined by the DRAM Base Address Register1 (DBA1) CSR.
If PM2 = 1, then the pin is used as BRG3/PA12 and may be bidirectional
5.4.4 CAS0 - DRAM Column Address Select Bit 0
If the PM3 bit of the MBCTRL = 0, this active low output signal is used to enable the DRAM
module upper byte (bits 15–8).
If PM3 = 1 then the pin is used for PB0/IACK7 and may be bidirectional.
5.4.5 CAS1- DRAM Column Address Select Bit 1
If the PM4 bit of the MBCTRL = 0, this active low output signal is used to enable the lower
byte (bits 7–0) of the DRAM module.
If PM4 = 1 then the pin is used for PB1/IACK6 and may be bidirectional.
5.4.6 DRAMRW- DRAM Read/Write
If the PM5 bit of the MBCTRL = 0, this pin is asserted low for a DRAM write cycle. It is
separate from the processor bus R/W signal to allow precharge to take place without regard
to the state of R/W.
If PM5 = 1 then the pin is used for PB2/IACK1 and may be bidirectional.
相關(guān)PDF資料
PDF描述
MC68302FC20CR2 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
MC68302FC16CR2 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132
MC68LC302PU20CT 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
MC68EN302PV25BT 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
MC68302PV33C 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68EN302PV20 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Multiprotocol Processor with Ethernet
MC68EN302PV20BT 功能描述:IC MPU MULTI-PROTOCOL 144-LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤
MC68EN302PV25 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Multiprotocol Processor with Ethernet
MC68EN302PV25BT 功能描述:IC MPU MULTI-PROTOCOL 144-LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤
MC68EN360AI25L 功能描述:微處理器 - MPU QUICC ETHRN RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*