參數(shù)資料
型號: MC68EN302CPV20BT
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù): 49/128頁
文件大小: 641K
代理商: MC68EN302CPV20BT
MC68EN302 Module Bus Controller
2-10
MC68EN302 REFERENCE MANUAL
MOTOROLA
reduced one extra clock. A0 is incremented one half clock earlier in this scheme to allow
sufficient address access in the second portion of the bus cycle. Figure 2-6 shows the fast
cycle read case, while Figure 2-7 shows the fast cycle write case. In order to use fast cycles
with SRAM, the CS signal is high between cycles, accommodating a write to SRAMs.
Figure 2-6. Fast Cycle Word Read with –1 Wait State
Figure 2-7. Fast Cycle Word Write with -1 Wait State
2.9.2 Bus Error Handling
Since the external bus may operate as an 8-bit bus, at the same time the internal bus
operates as 16-bits, a bus error passed from the external bus to the internal bus does not
specify which byte has been faulted. To assure that information is not lost, the Bus Error
S2
S3
S4
S5
S0
S1
CLOCK
S0
S1
S2
S3
ADDR23-1
ADDR0
AS/CS
RW
DATA
UDS/LDS
S2
S3
S4
S5
S0
S1
CLOCK
S0
S1
S2
S3
ADDR23-1
ADDR0
AS
RW
DATA
UDS/LDS
CS
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