![](http://datasheet.mmic.net.cn/30000/MC68307CFG16_datasheet_2368698/MC68307CFG16_102.png)
System Integration Module
MOTOROLA
MC68307 USER’S MANUAL
5-7
The default for each chip select is a 16-bit data-bus width. The BUSWx bits in the SCR
enable 8-bit data-bus width for each of the four chip select ranges. The initial bus width for
chip select 0 is selected by placing a logic 0 or 1 on the BUSW pin at reset, to specify 8-bit
or 16-bit wide data bus respectively. This allows a boot EPROM of either data bus width to
be used in any given system.
All external accesses which do not match one of the chip select address ranges use the
value of the EBUSW bit in the SCR to determine their data bus width.
NOTE
If byte operations are performed where 8-bit bus mode is used,
there is no difference in throughput compared to 16-bit bus
mode. However, if 32-bit long word or 16-bit word operations are
used over the 8-bit data bus (including all instruction fetches),
the performance is exactly half that of the equivalent speed 16-
bit-wide data bus.
5.1.2.2 PERIPHERAL CHIP SELECTS. Chip select 2 (CS2 signal) features a peripheral
chip select (PCS) mode, selected by setting the enable peripheral chip select (EPCS) bit in
the SCR. If this chip select is programmed with a block size of 64 Kbytes, and the EPCS bit
in the SCR set, then the CS2/CS2A pin, along with CS2B, CS2C, and CS2D (which are
multiplexed with port A input/output lines) function as four peripheral chip selects, each
gated to select a particular 16-Kbyte block within the programmed 64-Kbyte range.
For example, if the base address is programmed as $100000 with size $10000 (64K), and
the PCS mode is enabled, then the blocks are selected according to
Table 5-1:This feature is ideal for miscellaneous peripheral devices in the address space, even if they
only require one or two bytes per peripheral. If this feature is not enabled (refer to Section general-purpose programmable M68000-bus chip select, and the CS2B, CS2C and CS2D
signals are never asserted.
NOTE
Port A general-purpose I/O lines have programmable control
over their function on a bit by bit basis, via the port A control reg-
ister (PACNT). For example it is possible to use only CS2A and
CS2B, leaving the port A lines which would have been used by
CS2C and CS2D, to function as general-purpose I/O.
Table 5-1. Address Block Selection in Peripheral Chip Select Mode
Chip Select Pin
Address Block
A15
A14
Start Address
End Address
CS2A
$100000
$103FFF
0
CS2B
$104000
$107FFF
0
1
CS2C
$108000
$10BFFF
1
0
CS2D
$10C000
$10FFFF
1