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參數(shù)資料
| 型號(hào)： | MC68307FG16 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁(yè)數(shù)： | 189/264頁(yè) |
| 文件大小： | 949K |
| 代理商： | MC68307FG16 |
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Signal Description
MOTOROLA
MC68307 USER’S MANUAL
2-7
chip selects by programming, but it has the three extra enable outputs which are used to
further divide this address space. If they are used, each of the four peripheral enable outputs
decode fixed 16-Kbyte address ranges within the confines of the programmed range of CS2
(which should therefore be a block 64K bytes in size). Refer to Section 5.1.2.2 Peripheral
Chip Selects and Section 5.2.2 Chip Select Registers for details. The data bus width for
memory devices selected by this chip select is programmable, between 8- and 16-bit data,
in the system control register.
The CS2/CS2A chip select signal has its own pin on the MC68307, but the three extra
enable outputs CS2B, CS2C, CS2D are multiplexed with the port A input/output functions,
and require to be programmed to use these pins at cold reset. This is done by setting bits in
the port A control register (PACNT) as well as a bit in the system control register to enable
the peripheral address decoder. As port A defaults to an input port on cold reset, these three
additional peripheral chip select lines, if they are used, should have pullup resistors to
ensure peripherals are not accidentally enabled during system initialization.
When programmed as general-purpose input/output port lines, CS2B–CS2D function as
PA0–PA2.
2.2.4 Chip Select 3 (CS3)
This chip select output can be programmed to perform an 8051-compatible bus cycle rather
than a M68000 bus cycle. If 8051-compatible bus access is not required in a design, then
this signal can be programmed to be a general purpose chip-select output. The data bus
width for M68000-bus memory devices selected by this chip select is programmable,
between 8- and 16-bit data, in the system control register. If the 8051-compatible bus inter-
face is enabled, then the data-bus width for this chip select should be programmed to be 8
bits. The 8051-compatible bus has an address space (typically 64 Kbytes long, but not
restricted) which can be located anywhere in memory, as long as it does not overlap with
other programmed chip select ranges.
2.3 BUS CONTROL SIGNALS
These are signals that may be decoded or provided by external logic, to control the various
types of bus access which can occur.
The bus control signals are three-stated whenever the MC68307 is arbitrated off the bus by
an external bus master.
2.3.1 Data Transfer Acknowledge (DTACK)
This bidirectional, open-drain, active-low signal indicates that the data transfer has been
completed. DTACK is an output when it is generated internally by the programmable wait-
state generators in the chip-select logic (including CS3 for 8051-compatible bus accesses),
or during an access to internal peripheral registers. It is an input for all other M68000 bus
cycles, i.e., when the MC68307 accesses an external device not within the range of the chip-
select logic or when programmed to be generated externally for any particular chip-select.
In this case, external logic must assert it in order to complete the bus cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68307UM | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
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| MC68322FT20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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