參數(shù)資料
型號(hào): MC68307FG16
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100
封裝: PLASTIC, QFP-100
文件頁(yè)數(shù): 12/264頁(yè)
文件大?。?/td> 949K
代理商: MC68307FG16
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System Integration Module
5-14
MC68307 USER’S MANUAL
MOTOROLA
5.1.4.1 INTERRUPT CONTROLLER LOGIC. This block of logic coordinates all the
interrupt sources on the MC68307, gathering interrupt request signals from both the on-chip
peripheral modules and external inputs, prioritizing them and performing programmed IPL
requests to the EC000 core processor. When the EC000 core processor responds to a
request with an interrupt acknowledge cycle, as is standard in M68000 implementations, the
interrupt controller logic forwards the correct vector depending on the original source of the
interrupt. Software can clear pending interrupts from any source via the registers in the
interrupt controller logic, and can program the location of the block of vectors used for
interrupt sources via the programmable interrupt vector register (PIVR).
For an external interrupt interface, the interrupt controller logic provides two distinct facilities.
First is the nonmaskable interrupt input on the IRQ7 pin, which always causes an interrupt
priority level 7 request to the EC000 core processor. Assuming no other source is
programmed as a level 7 source, this input always obtains the immediate attention of the
core. For an interrupt to be successfully processed, RAM must be available for the stack,
and often this RAM is selected by one of the programmable chip selects. So upon system
startup there is a brief period where RAM is not available for the stack. To ensure no
problems resulting from interrupts (particularly IRQ7) during this period, there is an interlock
which prevents any interrupt from reaching the EC000 core processor until the first write
cycle to the PIVR. The user should ensure that both RAM chip selects and the system stack
are set up prior to this write operation.
The second of the external input methods is an 8-channel latched interrupt port, multiplexed
with the port B input/output pins. Each of the 8 inputs can be programmed with an IPL, and
each can have any pending interrupts cleared independently of the others.
The interrupt controller includes daisy-chaining functions in order to avoid contention when
the EC000 core processor issues an interrupt acknowledge cycle. So if more than one inter-
rupt source has the same IPL, they are daisy-chained in the following priority scheme:
IRQ7 Input
Highest Priority
INT1–INT8 Inputs
Timer 1Interrupt
Timer 2 Interrupt
UART Interrupt
M-Bus Interrupt
Lowest Priority
The priority within the eight latched interrupt inputs is that INT1 is the highest, and INT8 is
the lowest.
The block diagram of the interrupt controller is shown in Figure 5-4.
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