參數(shù)資料
型號： MC56F8014VFAE
廠商： Freescale Semiconductor
文件頁數(shù)： 88/124頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTRLR 32-LQFP
標準包裝： 250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
配用： DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
56F8014 Technical Data, Rev. 11
66
Freescale Semiconductor
1 = Timer Channel 3 enabled in Stop mode
6.3.1.2
Timer Channel 2 Stop Disable (TC2_SD)—Bit 14
This bit enables the operation of the Timer Channel 2 peripheral clock in Stop mode.
0 = Timer Channel 2 disabled in Stop mode
1 = Timer Channel 2 enabled in Stop mode
6.3.1.3
Timer Channel 1 Stop Disable (TC1_SD)—Bit 13
This bit enables the operation of the Timer Channel 1 peripheral clock in Stop mode.
0 = Timer Channel 1 disabled in Stop mode
1 = Timer Channel 1 enabled in Stop mode
6.3.1.4
Timer Channel 0 Stop Disable (TC0_SD)—Bit 12
This bit enables the operation of the Timer Channel 0 peripheral clock in Stop mode.
0 = Timer Channel 0 disabled in Stop mode
1 = Timer Channel 0 enabled in Stop mode
6.3.1.5
SCI Stop Disable (SCI_SD)—Bit 11
This bit enables the operation of the SCI peripheral clock in Stop mode. This is recommended for use in
LIN mode so that the SCI can generate interrupts and recover from Stop mode while the LIN interface is
in Sleep mode and using Stop mode to reduce power consumption.
0 = SCI disabled in Stop mode
1 = SCI enabled in Stop mode
6.3.1.6
Reserved—Bit 10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.1.7
Timer Channel 3 Input (TC3_INP)—Bit 9
This bit selects the input of Timer Channel 3 to be from the PWM sync signal or GPIO pin.
1 = Timer Channel 3 Input from PWM sync signal
0 = Timer Channel 3 Input controlled by SIM_GPS register CFG_B3 and CFG_A5 fields
6.3.1.8
Reserved—Bits 8–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.1.9
OnCE Enable (ONCEEBL)—Bit 5
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.3.1.10
Software Reset (SWRST)—Bit 4
Writing 1 to this field will cause the part to reset.
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