參數(shù)資料
型號： MC56F8014VFAE
廠商： Freescale Semiconductor
文件頁數(shù)： 79/124頁
文件大小： 0K
描述： IC DIGITAL SIGNAL CTRLR 32-LQFP
標準包裝： 250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
配用： DEMO56F8014-E-ND - BOARD DEMO MC56F8014 W/UNIV PS
DEMO56F8014-ND - BOARD DEMO MC56F8014 W/US PS
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
DEMO56F8014-EE-ND - BOARD DEMO FOR 56F8014
56F8014 Technical Data, Rev. 11
58
Freescale Semiconductor
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority
level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to
the vector table.
5.5.11
Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Figure 5-13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
5.5.11.1
Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.5.12
Fast Interrupt 1 Vector Address High Register (FIVAH1)
Figure 5-14 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.5.12.1
Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.5.12.2
Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.5.13
IRQ Pending Register 0 (IRQP0)
Figure 5-15 IRQ Pending Register 0 (IRQP0)
5.5.13.1
IRQ Pending (PENDING)—Bits 15–1
This register combines with IRQP1 and IRQP2 to represent the pending IRQs for interrupt vector numbers
2 through 45.
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
FAST INTERRUPT 1 VECTOR ADDRESS LOW
Write
RESET
00000
0000000
0000
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
Write
RESET
00000
0000000
0000
Base + $C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
PENDING[16:2]
1
Write
RESET
11111
1111111
1111
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