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參數(shù)資料
| 型號： | MC10SX1125A |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 622Mb/s Fiber Optic Post Amplifier(622Mb/s 光纖后置放大器) |
| 中文描述： | 622Mb / s的光纖后置放大器（622Mb / s的光纖后置放大器） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 96K |
| 代理商： | MC10SX1125A |
MC10SX1125A
http://onsemi.com
3
Coupling Capacitors
The SX1125A inputs must be AC coupled to allow proper
operation of the offset correction function. The coupling
capacitors, Cin, must be large enough to pass the lowest input
frequency of interest.
Cin
1
2
(Rin) (flow)
where
Rin= input resistance = 5000
flow= lowest frequency.
Auto–zero Capacitors
A feedback amplifier is used to cancel the offset voltage
of the forward signal path, so the input to the internal ECL
comparator is at its toggle point in the absence of any input
signal. The time constant of the cancelling circuitry is set by
an external capacitor (CAZ) connected between Pins 1 and
2. The formula for the calculation of the auto–zero capacitor
is:
CAZ
150
2
(RAZ) (flow)
where
RAZ= internal driving impedance = 290k
flow= lowest frequency.
Input Signal Level Detector
The SX1125A allows for user programmable input signal
level–detection and can automatically disable the switching
of its ECL data output if the input level is below a set
threshold. This prevents the outputs from reacting to noise
in the absence of a valid input signal, and ensures that data
will only be transmitted when the signal–to–noise ratio is
sufficient for low bit–error–rate system operation.
Complimentary ECL flags (LOS and LOSB) indicate
whether the input signal is above or below the desired
threshold level. In the level detect system, the input signal
is amplified and rectified before being compared to a
programmable reference. A filter is included to prevent
noise spikes from triggering the level–detector. The filter
has a nominal 1
μ
s time constant, and additional filtering can
be achieved by using an external capacitor (CLD) from Pin
7 to VCCA (the internal driving impedance is nominally
28k). The formula for the calculation of the CLD capacitor
is:
CLD
t
RZ
where
RZ= internal driving impedance = 28k
t = LOS filter time constant.
DC CHARACTERISTICS
(GNDA = GNDE = Ground; VCCA = VCCE = 4.5V to 5.5V)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIN
VOS
VN
VTH
VHYS
IIH
ICC
1. This device functions with Vinmin = 6mVP–P, but with increased BER (See BER data).
2. This device has an anomoly in VHYS when 0.65 < VSET < 0.75V. Operation in this region is not recommended.
Input Signal Voltage (Din)
Input Offset Voltage
Single-Ended
0.008
1.5
VP-P
μ
V
Note 1.
50
Input RMS Noise
225
μ
V
Input Level Detect Programmability
8.0
20
mVP-P
dB
Level Detect Hysteresis
1.5
2.5
7.0
Note 2.
Input HIGH Current Disable
150
μ
A
Power Supply Current
33
45
mA
0
0.3
5
10
15
20
25
30
35
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
Vset (V)
V
Figure 2. LOS versus Vset
(TA = 25
°
C)
0
0.3
1
2
3
4
5
6
7
8
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
Vset (V)
(
H
V
Figure 3. LOS Hysteresis
(TA = 25
°
C)
I
Input detect
level (LOS 1 0)
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