參數(shù)資料
型號(hào): MC10SX1125A
廠商: ON SEMICONDUCTOR
英文描述: 622Mb/s Fiber Optic Post Amplifier(622Mb/s 光纖后置放大器)
中文描述: 622Mb / s的光纖后置放大器(622Mb / s的光纖后置放大器)
文件頁(yè)數(shù): 2/8頁(yè)
文件大?。?/td> 96K
代理商: MC10SX1125A
MC10SX1125A
http://onsemi.com
2
FUNCTION TABLE
Pin
Function
CAZN
CAZP
GNDA
Auto-zero capacitor pin. A capacitor between this pin and CAZP cancels any offset inherent to the limiting amplifier.
Auto-zero capacitor pin. A capacitor between this pin and CAZN cancels any offset inherent to the limiting amplifier.
Analog ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the
same potential.
Din, Din
VCCA
Differential data input.
Analog power supply pin. +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at
the same potential.
CLD
Disable
Filter capacitor for the level detect comparator. Capacitor should be connected to VCCA.
When asserted LOW, or left open and pulled LOW via the input pulldown resistor, the output buffer will be enabled and
will respond to the input stimulus on the Din input. Forcing Disable HIGH will force the Dout output LOW and its
complimentary output HIGH.
LOS
Loss of signal. This output will go HIGH when the input signal falls below (Vset/100) mVP-P.
Digital ground pin. Ground for PECL operation or –5.2V for standard ECL operation. GNDA and GNDE must be at the
same potential.
GNDE
Dout, Dout
VCCE
Differential data outputs.
Digital power supply pin. +5V for PECL operation or ground for standard ECL operation. VCCA and VCCE must be at the
same potential.
Vref
Vset
Reference voltage for threshold level set voltage division network (2.64V).
Input threshold level detect setting input. Input generated from voltage divider between Vref and GNDA.
Figure 1. Typical Operating Circuit
16
1
CAZN
Vset
15
2
CAZP
Vref
14
3
GNDA
VCCE
13
4
Din
Dout
12
5
Din
Dout
11
6
VCCA
GNDE
10
7
CLD
LOS
9
8
Disable
LOS
R1
R2
50
DATA OUT
50
5V
3V
50
LEVEL
DETECT OUT
50
Cbypass
CAZ
Cin
Cin
DATA IN
5V
CAZ
Cbypass
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