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參數(shù)資料
| 型號： | MB95F564KPF-G-JNE2 |
| 廠商： | Fujitsu Semiconductor America Inc |
| 文件頁數(shù)： | 66/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 20KB FLASH 20TSSOP |
| 標準包裝： | 1,225 |
| 系列： | 8FX MB95560H |
| 核心處理器： | F²MC-8FX |
| 芯體尺寸： | 8-位 |
| 速度： | 16MHz |
| 連通性： | LIN，UART/USART |
| 外圍設備： | LVD. POR，PWM，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲器容量： | 20KB（20K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 496 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.4 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x8/10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 托盤 |
| 其它名稱： | 865-1239 |
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2010 Microchip Technology Inc.
DS70135G-page 69
dsPIC30F4011/4012
9.4
Timer Interrupt
The 16-bit timer has the ability to generate an interrupt
on period match. When the timer count matches the
Period register, the T1IF bit is asserted and an interrupt
will be generated, if enabled. The T1IF bit must be
cleared in software. The Timer Interrupt Flag, T1IF, is
located in the IFS0 control register in the interrupt
controller.
When the Gated Time Accumulation mode is enabled,
an interrupt will also be generated on the falling edge of
the gate signal (at the end of the accumulation cycle).
Enabling an interrupt is accomplished via the respec-
tive Timer Interrupt Enable bit, T1IE. The timer interrupt
enable bit is located in the IEC0 Control register in the
interrupt controller.
9.5
Real-Time Clock
Timer1, when operating in Real-Time Clock (RTC)
mode, provides time-of-day and event time-stamping
capabilities. Key operational features of the RTC are:
Operation from 32 kHz LP oscillator
8-bit prescaler
Low power
Real-Time Clock interrupts
These operating modes are determined by setting the
appropriate bit(s) in the T1CON Control register
FIGURE 9-2:
RECOMMENDED
COMPONENTS FOR
TIMER1 LP OSCILLATOR
REAL-TIME CLOCK (RTC)
9.5.1
RTC OSCILLATOR OPERATION
When TON = 1, TCS = 1 and TGATE = 0, the timer
increments on the rising edge of the 32 kHz LP oscilla-
tor output signal, up to the value specified in the Period
register, and is then reset to ‘0’.
The TSYNC bit must be asserted to a logic ‘0’
(Asynchronous mode) for correct operation.
Enabling LPOSCEN (OSCCON<1>) will disable the
normal Timer and Counter modes and enable a timer
carry-out wake-up event.
When the CPU enters Sleep mode, the RTC will con-
tinue to operate, provided the 32 kHz external crystal
oscillator is active and the control bits have not been
changed. The TSIDL bit should be cleared to ‘0’ in
order for RTC to continue operation in Idle mode.
9.5.2
RTC INTERRUPTS
When an interrupt event occurs, the respective Timer
Interrupt Flag, T1IF, is asserted and an interrupt will be
generated, if enabled. The T1IF bit must be cleared in
software. The respective Timer Interrupt Flag, T1IF, is
located in the IFS0 Status register in the interrupt
controller.
Enabling
an
interrupt
is
accomplished
via
the
respective Timer Interrupt Enable bit, T1IE. The Timer
Interrupt Enable bit is located in the IEC0 control
register in the interrupt controller.
SOSCI
SOSCO
R
C1
C2
dsPIC30FXXXX
32.768 kHz
XTAL
C1 = C2 = 18 pF; R = 100K
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