參數(shù)資料
型號: MB95F564KPF-G-JNE2
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 59/84頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 20KB FLASH 20TSSOP
標準包裝: 1,225
系列: 8FX MB95560H
核心處理器: F²MC-8FX
芯體尺寸: 8-位
速度: 16MHz
連通性: LIN,UART/USART
外圍設(shè)備: LVD. POR,PWM,WDT
輸入/輸出數(shù): 17
程序存儲器容量: 20KB(20K x 8)
程序存儲器類型: 閃存
RAM 容量: 496 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 托盤
其它名稱: 865-1239
dsPIC30F4011/4012
DS70135G-page 62
2010 Microchip Technology Inc.
FIGURE 8-2:
BLOCK DIAGRAM OF A SHARED PORT STRUCTURE
8.2
Configuring Analog Port Pins
The use of the ADPCFG and TRIS registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bit set (input). If the TRIS bit is cleared
(output), the digital output level (VOH or VOL) will be
converted.
When reading the PORT register, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as digital inputs will not convert an ana-
log input. Analog levels on any pin that is defined as a
digital input (including the ANx pins), may cause the
input buffer to consume current that exceeds the
device specifications.
8.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP.
EXAMPLE 8-1:
PORT WRITE/READ
EXAMPLE
Q
D
CK
WR LAT +
TRIS Latch
I/O Pad
WR PORT
Data Bus
Q
D
CK
Data Latch
Read LAT
Read PORT
Read TRIS
1
0
1
0
WR TRIS
Peripheral Output Data
Peripheral Input Data
I/O Cell
Peripheral Module
Peripheral Output Enable
PIO Module
Output Multiplexers
Input Data
Peripheral Module Enable
Output Enable
Output Data
MOV
0xFF00, W0
; Configure PORTB<15:8>
; as inputs
MOV
W0, TRISBB
; and PORTB<7:0> as outputs
NOP
; Delay 1 cycle
BTSS PORTB, #13
; Next Instruction
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