參數(shù)資料
型號: MB95F564KPF-G-JNE2
廠商: Fujitsu Semiconductor America Inc
文件頁數(shù): 64/84頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 20KB FLASH 20TSSOP
標(biāo)準(zhǔn)包裝: 1,225
系列: 8FX MB95560H
核心處理器: F²MC-8FX
芯體尺寸: 8-位
速度: 16MHz
連通性: LIN,UART/USART
外圍設(shè)備: LVD. POR,PWM,WDT
輸入/輸出數(shù): 17
程序存儲器容量: 20KB(20K x 8)
程序存儲器類型: 閃存
RAM 容量: 496 x 8
電壓 - 電源 (Vcc/Vdd): 2.4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x8/10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 托盤
其它名稱: 865-1239
2010 Microchip Technology Inc.
DS70135G-page 67
dsPIC30F4011/4012
9.0
TIMER1 MODULE
This section describes the 16-bit general purpose
Timer1 module and associated operational modes.
Figure 9-1 depicts the simplified block diagram of the
16-bit Timer1 module.
The following sections provide a detailed description,
including setup and control registers, along with asso-
ciated block diagrams for the operational modes of the
timers.
The Timer1 module is a 16-bit timer which can serve as
the time counter for the Real-Time Clock, or operate as
a free-running, interval timer/counter. The 16-bit timer
has the following modes:
16-bit Timer
16-bit Synchronous Counter
16-bit Asynchronous Counter
Further, the following operational characteristics are
supported:
Timer gate operation
Selectable prescaler settings
Timer operation during CPU Idle and Sleep
modes
Interrupt on 16-bit Period register match or falling
edge of external gate signal
These operating modes are determined by setting the
appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1
presents a block diagram of the 16-bit timer module.
16-bit Timer Mode: In the 16-bit Timer mode, the timer
increments on every instruction cycle up to a match
value, preloaded into the Period register, PR1, then
resets to 0 and continues to count.
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the TSIDL (T1CON<13>)
bit = 0. If TSIDL = 1, the timer module logic will resume
the incrementing sequence upon termination of the
CPU Idle mode.
16-bit Synchronous Counter Mode: In the 16-bit
Synchronous Counter mode, the timer increments on
the rising edge of the applied external clock signal,
which is synchronized with the internal phase clocks.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
When the CPU goes into the Idle mode, the timer will
stop incrementing unless the respective TSIDL bit = 0.
If TSIDL = 1, the timer module logic will resume the
incrementing sequence upon termination of the CPU
Idle mode.
16-bit Asynchronous Counter Mode: In the 16-bit
Asynchronous Counter mode, the timer increments on
every rising edge of the applied external clock signal.
The timer counts up to a match value preloaded in PR1,
then resets to 0 and continues.
When the timer is configured for the Asynchronous mode
of operation, and the CPU goes into the Idle mode, the
timer will stop incrementing if TSIDL = 1.
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
dsPIC30F
Family
Reference
Manual
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Reference Manual” (DS70157).
Note:
Timer1 is a ‘Type A’ timer. Please refer to
the specifications for a Type A timer in
of this document.
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