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參數(shù)資料
| 型號： | MAXADCLITE+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/22頁 |
| 文件大小： | 0K |
| 描述： | KIT EVALUATION FOR MAX11645 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 94.4k |
| 數(shù)據(jù)接口： | USB |
| 輸入范圍： | ±VREF/2 |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | MAX11645 |
| 已供物品： | 板，軟件 |
MAX11644/MAX11645
Low-Power, 1-/2-Channel, I2C, 12-Bit ADCs
in Ultra-Tiny 1.9mm x 2.2mm Package
______________________________________________________________________________________
17
External Clock
When configured for external clock mode (CLK = 1),
the MAX11644/MAX11645 use the SCL as the conver-
sion clock. In external clock mode, the MAX11644/
MAX11645 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later, the analog signal is acquired
and the conversion begins. Unlike the internal clock
mode, converted data is available immediately after the
first four empty high bits. The device continuously con-
verts input channels dictated by the scan mode until
given a not-acknowledge. There is no need to read-
dress the device with a read command to obtain new
conversion results (see Figure 11).
The conversion must complete in 1ms, or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60μs.
The MAX11644/MAX11645 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps, internal clock mode is recom-
mended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. The scanned results are written to memo-
ry in the same order as the conversion. Read the results
from memory in the order they were converted. Each
result needs a 2-byte transmission; the first byte begins
with 4 empty bits, during which SDA is left high. Each
byte has to be acknowledged by the master or the mem-
ory transmission is terminated. It is not possible to read
the memory independently of conversion.
SLAVE ADDRESS
tCONV1
tACQ1
tACQ2
tCONVN
tACQN
tCONV
tACQ
NUMBER OF BITS
1
8
A
1
S
1
A
71 1
R
S
1
71 1
R
P OR Sr
1
8
A
1
A
8
A
8
B) SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
SLAVE ADDRESS
P OR Sr
RESULT (8 LSBs)
8
A
1
RESULT (4 MSBs)
A) SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
RESULT 1 (4 MSBs)
RESULT 2 (8 LSBs)
RESULT N (8 LSBs)
A
1
8
RESULT N (4 MSBs)
A
Figure 11. External Clock Mode Read Cycle
SCAN1
SCAN0
SCANNING CONFIGURATION
0
Scans up from AIN0 to the input selected by CS0.
0
1
Converts the input selected by CS0 eight times (see Tables 3 and 4).*
1
0
Reserved. Do not use.
1
Converts the input selected by CS0.*
*
When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not-acknowledge occurs.
Table 5. Scanning Configuration
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| MAXADCLITE# | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX11645 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAXADCLITE+ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 MAX11645 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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| MAX-B570 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:THREE-CD CHANGER MINI-COMPACT SYSTEM CD-R/RW PLAYBACK |
| MAXC001 | 制造商:Maxim Integrated Products 功能描述: |
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