參數(shù)資料
型號: MAX9850ETI
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 消費家電
英文描述: Stereo Audio DAC with DirectDrive Headphone Amplifier
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC28
封裝: 5 X 5 MM, 0.80 MM PITCH, MO-220WHHD-1, TQFN-28
文件頁數(shù): 30/36頁
文件大?。?/td> 956K
代理商: MAX9850ETI
M
Start and Stop Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 6). A START
condition from the master signals the beginning of a
transmission to the MAX9850. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9850 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition. For
proper operation, do not send a STOP condition during
the same SCL high pulse as the START condition.
Slave Address
The MAX9850 is programmable to one of three slave
addresses (see Table 23). These slave addresses are
unique device IDs. Connect ADD to GND, AV
DD
, or
SDA to set the I
2
C slave address. The address is
defined as the seven most significant bits (MSBs) fol-
lowed by the Read/
Write
bit. Set the Read/
Write
bit to 1
to configure the MAX9850 to read mode. Set the
Read/
Write
bit to 0 to configure the MAX9850 to write
mode. The address is the first byte of information sent to
the MAX9850 after the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9850 uses to handshake receipt of each byte of
data when in write mode (see Figure 7). The MAX9850
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication.
The master pulls down SDA during the 9th clock cycle to
acknowledge receipt of data when the MAX9850 is in
read mode. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not-
acknowledge is sent when the master reads the final byte
of data from the MAX9850, followed by a STOP condition.
Stereo Audio DAC with DirectDrive
Headphone Amplifier
30
______________________________________________________________________________________
SCL
SDA
S
Sr
P
Figure 6. START, STOP, and REPEATED START Conditions
Table 23. MAX9850 Address Map
MAX9850 SLAVE ADDRESS
A4
A3
1
0
1
0
1
0
ADD
A6
0
0
0
A5
0
0
0
A2
0
0
0
A1
0
0
1
A0
0
1
1
R/
W
X
X
X
GND
AV
DD
SDA
X = Don’t Care.
1
SCL
START
CONDITION
SDA
2
8
9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 7. Acknowledge
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MAX9850ETI+TG47 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC Stereo Audio DAC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel
MAX9850ETI-T 制造商:Maxim Integrated Products 功能描述:STEREO AUDIO DAC WITH DIRECTDRIVE HEADPHONE A - Tape and Reel