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參數(shù)資料
| 型號： | MAX199BMYI |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Multi-Range (【4V, 【2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP28 |
| 封裝： | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MAX199BMYI |
M
Multi-Range (±4V, ±2V, +4V, +2V ),
+5V S upply, 12-Bit DAS with 8+4 Bus Interfac e
_______________________________________________________________________________________
5
Note 1:
Accuracy specifications tested at V
DD
= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±4.096V input range.
External reference: V
REF
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Ground “on” channel; sine wave applied to all “off” channels.
Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Guaranteed by design. Not tested.
Use static loads only.
Tested using internal reference.
PSRR measured at full-scale. V
DD
= 4.75V to 5.25V.
External acquisition timing: starts at rising edge of WR with control bit ACQMOD = low; ends at rising edge of WR with
ACQMOD = high.
Note 10:
Not subject to production testing. Provided for design guidance only.
Note 11:
All input control signals specified with t
R
= t
F
= 5ns from a voltage level of 0.8V to 2.4V.
Note 12:
t
DO
and t
DO1
are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
or 2.4V.
Note 13:
t
TR
is defined as the time required for the data lines to change by 0.5V.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
TIMING CHARACTERISTICS
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
(Note 13)
ns
ns
70
120
CONDITIONS
t
TR
t
INT1
RD High to Output Disable
RD Low to INT High Delay
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
80
0
0
0
0
t
CS
t
WR
t
CSWS
t
CSWH
t
CSRS
t
CSRH
t
CWS
t
CWH
t
DS
t
DH
t
DO
CS Pulse Width
WR Pulse Width
CS to WR Setup Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
CS to WR Hold Time
CS to RD Setup Time
CS to RD Hold Time
CLK to WR Setup Time
100
50
CLK to WR Hold Time
Data Valid to WR Setup
60
0
Data Valid to WR Hold
RD Low to Output Data Valid
Figure 2, C
L
= 100pF (Note 12)
Figure 2, C
L
= 100pF (Note 12)
120
ns
120
t
DO1
HBEN High or HBEN Low to
Output Valid
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