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參數(shù)資料
| 型號： | MAX199BMYI |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Multi-Range (【4V, 【2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP28 |
| 封裝： | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MAX199BMYI |
M
How to S tart a Conversion
Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX199 for
either unipolar or bipolar input range. A write pulse (WR
+ CS) can either start an acquisition interval or initiate a
combined acquisition plus conversion. The sampling
interval occurs at the end of the acquisition interval.
The ACQMOD bit in the input control byte offers two
options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.
Writing a new control byte during the conversion cycle
will abort the conversion in progress and start a new
acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3μs with
f
CLK
= 2MHz) ends. See Figure 5.
External Acquisition
Use the external acquisition timing mode for precise con-
trol of the sampling aperture and/or independent control of
acquisition and conversion times. The user controls acqui-
sition and start-of-conversion with two separate write puls-
es. The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0, terminates acquisi-
tion and starts conversion on WR’s rising edge (Figure 6).
However, if the second control byte contains ACQMOD =
1, an indefinite acquisition interval is restarted.
The address bits for the input mux must have the same
values on the first and second write pulses. Power-
down mode bits (PD0, PD1) can assume new values on
the second write pulse (see Power-Down Mode).
Multi-Range (±4V, ±2V, +4V, +2V ),
+5V S upply, 12-Bit DAS with 8+4 Bus Interfac e
10
______________________________________________________________________________________
t
CS
t
CSWS
t
WR
t
ACQI
t
CONV
t
DH
t
DS
t
INT1
t
D0
t
D01
t
TR
HIGH-Z
HIGH-Z
t
CSRS
t
CSRH
CS
WR
D7–D0
INT
RD
HBEN
DOUT
ACQMOD ="0"
HIGH / LOW
HIGH / LOW
CBYTE
t
CSWH
Figure 5. Conversion Timing Using Internal Acquisition Mode
Table 5. Data-Bus Output
PIN
D0
D1
D2
D3
D4
D5
D6
D7
HBEN = LOW
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
HBEN = HIGH
B8
B9
B10
B11 (MSB)
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
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