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參數(shù)資料
| 型號： | MAX199BMYI |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Multi-Range (【4V, 【2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP28 |
| 封裝： | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 165K |
| 代理商： | MAX199BMYI |
M
Multi-Range (±4V, ±2V, +4V, +2V ),
+5V S upply, 12-Bit DAS with 8+4 Bus Interfac e
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7μF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Internal acquisition
3.0
3.0
5.0
External reference = 4.096V
Internal reference
After FULLPD or STBYPD
External CLK
Internal CLK, C
CLK
= 100pF
External CLK
Internal CLK, C
CLK
= 100pF
External acquisition (Note 9)
CONDITIONS
Full power-down mode (FULLPD) (Note 7)
5
μs
3.0
t
ACQI
Acquisition Time
LSB
±
1
/
2
PSRR
Power-Supply Rejection Ratio
(Note 8)
t
ACQE
μs
V
4.75
5.25
18
10
V
DD
Supply Voltage
6.0
6.0
t
CONV
Conversion Time
7.7
10.0
100
To 0.1mV, REF
bypass capacitor
fully discharged
ms
8
Reference Buffer Settling
60
120
60
Normal mode, bipolar ranges
Normal mode, unipolar ranges
Standby power-down (STBYPD)
700
850
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
mA
I
DD
Supply Current
6
μA
±
1
/
2
C
CLK
= 100pF
MHz
MHz
1.25
0.1
1.56
2.00
2.0
f
CLK
f
CLK
Internal Clock Frequency
External Clock Frequency Range
External CLK
Internal CLK
Power-up (Note 10)
μs
200
Bandgap Reference
Start-Up Time
ksps
Throughput Rate
62
C
REF
= 4.7μF
C
REF
= 33μF
V
V
2.4
V
INH
V
INL
I
IN
C
IN
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS
(D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
0.8
±10
15
V
IN
= 0V or V
DD
(Note 5)
μA
pF
V
DD
= 4.75V, I
SINK
= 1.6mA
V
DD
= 4.75V, I
SOURCE
= 1mA
(Note 5)
V
V
pF
0.4
V
OL
V
OH
C
OUT
Output Low Voltage
Output High Voltage
Three-State Output Capacitance
V
DD
- 1
15
POWER REQUIREMENTS
TIMING
DIGITAL INPUTS
(D7–D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11)
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