參數(shù)資料
型號(hào): MAX1816ETM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: Replaced by TMS320VC5506 : Digital Signal Processors 144-LQFP
中文描述: DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, CQCC48
封裝: 7 X 7 MM, 0.80 MM HEIGHT, THIN, QFN-48
文件頁數(shù): 44/49頁
文件大小: 983K
代理商: MAX1816ETM
M
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
44
______________________________________________________________________________________
3) A third pole is set by the linear regulator
s feedback
resistance and the capacitance between LINFB
and GND, including the stray capacitance:
4) If the second and third poles occur well after unity
gain crossover, the linear regulator remains stable:
f
POLE(CEB)
> 2f
POLE(CLDO)
A
V(LDO)
However, if the ESR zero occurs before the unity gain
crossover, cancel the zero with the feedback pole by
changing circuit components such that:
For most applications where ceramic capacitors are
used, the ESR zero always occurs after the crossover.
Output Capacitor Selection
Typically, more output capacitance provides the best
performance, since this also reduces the output voltage
drop immediately after a load transient. Connect at
least a 10μF capacitor between the linear regulator
s
output and ground, as close to the external pass tran-
sistor as possible. Depending on the selected pass
transistor, larger capacitor values may be required
for stability (see the
Linear Regulator Stability
Requirements
section). Furthermore, the output capaci-
tor
s ESR affects stability. Use output capacitors with an
ESR less than 200m
to ensure stability and optimum
transient response. Once the minimum capacitor value
for stability is determined, verify that the linear regula-
tor
s output does not contain excessive noise. Although
adequate for stability, small capacitor values can pro-
vide too much bandwidth, making the linear regulator
sensitive to noise. Larger capacitor values reduce the
bandwidth, thereby reducing the regulator
s noise sen-
sitivity.
Applications Information
Voltage Positioning
Powering new mobile processors requires new tech-
niques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
allows a larger step down when the output current sud-
denly increases, and regulating at the lower output volt-
age under load allows a larger step up when the output
current suddenly decreases. Allowing a larger step size
means that the output capacitance can be reduced
and the capacitor
s ESR can be increased.
Adding a series output resistor positions the full-load
output voltage below the actual DAC programmed volt-
age. Connect FB directly to the inductor side of the
voltage-positioning resistor (R1, 1m
). The other side
of the voltage-positioning resistor should be connected
directly to the output filter capacitor with a short, wide
PC board trace. With the gain pin floating (GAIN = 2), a
20A full-load current causes a 40mV drop in the output.
This 40mV is a -3.2% droop.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in R1.
For a nominal 1.25V, 20A output, reducing the output
voltage by 3.2% gives an output voltage of 1.21V and
an output current of 19.4A. Given these values, CPU
power consumption is reduced from 25W to 23.5W. The
additional power consumption of R1 is:
1m
(19.4A)
2
= 0.38W
And the overall power savings is as follows:
25W - (23.5W + 0.38W)= 1.12W
In effect, 1.5W of CPU dissipation is saved, and the
power supply dissipates some of the power savings,
but both the net savings and the transfer of dissipation
away from the hot CPU are beneficial.
High-Current Master-Slave Applications
The MAX1816/MAX1994 can be used in high-current
applications using additional slave regulators. Figure 2
illustrates a 40A master-slave application using this
technique. The MAX1994 is placed in forced PWM
mode to simplify operation with the slave. Refer to the
MAX1980 data sheet for a detailed description of the
master-slave architecture and how to configure correctly
the slave circuit.
Dropout Performance
The output voltage adjustment range for continuous-
conduction operation is restricted by the nonadjustable
500ns (max) minimum off-time one-shot (375ns max at
550kHz and 1000kHz). For best dropout performance,
use the slower (200kHz) on-time settings.
f
C
POLE FB
LDO ESR
(
)
1
2
π
f
C
R
(
R
POLE FB
FB
(
)
||
)
=
1
2
8
9
π
f
C
R
(
R
R
2
V h
C
POLE CEB
EB
EB
IN
EB LOAD
EB EB T FE
π
(
)
||
)
=
=
+
1
2
π
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