M
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________
43
where I
LIMIT(HIGH)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation.
The MOSFETs must have a good-sized heat sink to
handle the overload power dissipation. If short-circuit
protection without overload protection is enough, a
normal I
LOAD
value can be used for calculating compo-
nent stresses.
Choose a Shottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency is not critical.
Linear Regulator
Design Procedure
Output Voltage Selection
Adjust the linear regulator
’
s output voltage by connect-
ing a resistive voltage-divider from V
LIN
to AGND with
the center tap connected to LINFB (Figure 1). Select R9
in the range of 10k
to 100k
. Calculate R8 with the
following equation:
R8 = R9 [(V
LIN
/ 1.00V) - 1]
Pass Transistor Selection
The PNP pass transistor must meet specifications for
current gain (h
FE
), input capacitance, emitter-collector
saturation voltage, and power dissipation. The
transistor
’
s current gain limits the guaranteed maximum
output current to:
where I
DRV
is the minimum base-drive current, and R
EB
is the pullup resistor connected between the transis-
tor
’
s emitter and base. Furthermore, the transistor
’
s cur-
rent gain increases the linear regulator
’
s DC loop gain
(see the
Linear Regulator Stability Requirements
sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 300A/A at
the maximum output current are not recommended.
The transistor
’
s input capacitance and input resistance
also create a second pole, which could be low enough
to make the output unstable when heavily loaded.
The transistor
’
s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Alternatively, the package
’
s power dissipation could
limit the usable maximum input-to-output voltage differ-
ential. The maximum power dissipation capability of the
transistor
’
s package and mounting must exceed the
actual power dissipation in the device.
The power dissipation equals the maximum load current
times the maximum input-to-output voltage differential:
P = I
LOAD(MAX)
x (V
LDOIN
- V
LIN
) = I
LOAD(MAX)
x V
CE
Linear Regulator Stability Requirements
The MAX1816/MAX1994 linear-regulator controller uses
an internal transconductance amplifier to drive an
external pass transistor. The transconductance amplifi-
er, the pass transistor, the emitter-base resistor, and
the output capacitor determine the loop stability. If the
output capacitor and pass transistor are not properly
selected, the linear regulator is unstable.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor
’
s base cur-
rent. Since the output voltage is a function of the load
current and load resistance, the total DC loop gain is
approximately:
where V
T
is 26mV at room temperature, I
BIAS
is the cur-
rent though the emitter-base resistor (R
EB
), and V
REF
=
1.0V. This bias resistor is typically 220
, providing
approximately 3.2mA of bias current.
The output capacitor and the load resistance create the
dominant pole in the system. However, the pass tran-
sistor
’
s input capacitance creates a second pole in the
system. Additionally, the output capacitor
’
s ESR gener-
ates a zero. To achieve stable operation, use the follow-
ing equations to verify that the linear regulator is
properly compensated:
1) First, determine the dominant pole set by the linear
regulator
’
s output capacitor and the load resistor:
The unity gain crossover of the linear regulator is:
f
CROSSOVER
= A
V(LDO)
f
POLE(CLDO)
2) Next, determine the second pole set by the emitter-
base capacitance (including the transistor
’
s input
capacitance), the transistor
’
s input resistance, and
the emitter-base pullup resistor:
f
C
I
π
C
POLE CLDO
(
LDO LOAD
LOAD MAX
LDO LDO
)
(
)
=
=
1
2
2
π
A
V
V
I
I
V LDO
(
REF
T
BIAS FE
LOAD
)
.
=
+
1
5 5
I
I
V
R
h
LOAD MAX
DRV
EB
EB
FE MIN
(
(
)
)
=