參數(shù)資料
型號: MAX1816ETM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: Replaced by TMS320VC5506 : Digital Signal Processors 144-LQFP
中文描述: DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, CQCC48
封裝: 7 X 7 MM, 0.80 MM HEIGHT, THIN, QFN-48
文件頁數(shù): 21/49頁
文件大?。?/td> 983K
代理商: MAX1816ETM
M
Dual Step-Down Controllers Plus Linear-
Regulator Controller for Notebook Computers
______________________________________________________________________________________
21
PIN
14
15
16
17
NAME
D1
D2
D3
D4
FUNCTION
VID Code Input
VID Code Input
VID Code Input
VID Code Input. D4 is the most significant bit (MSB).
Suspend Mode Voltage-Select Input. S0 and S1 are four-level logic inputs that select the suspend mode
VID code for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered
to the DAC overriding any other voltage setting (see the
DAC Inputs and Internal Multiplexer
section).
Suspend Mode Voltage-Select Input. S0 and S1 are four-level logic inputs that select the suspend mode
VID code for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered
to the DAC overriding any other voltage setting (see the
DAC Inputs and Internal Multiplexer
section).
Combined Shutdown and Skip-Mode Control Input for BUCK1. Always start BUCK2 before starting BUCK1.
Connect SKP1/
SDN
to V
CC
or drive the pin above 2.8V with external 3.3V-powered CMOS logic for normal
PFM/PWM operation. Connect SKP1/
SDN
to GND or drive the pin below 0.5V to shut down BUCK1. In
shutdown mode, DL1 is forced to V
DD
in order to enforce overvoltage protection when the regulator is
powered down. Leave SKP1/
SDN
floating for the low-noise forced PWM operation. Low-noise forced-PWM
mode causes the inductor current to reverse at light loads and suppresses pulse-skipping operation.
SKP1/
SDN
can also be used to disable both over- and undervoltage protection circuits and clear the fault
latch. This test mode is enabled by forcing the pin to 10.8V < V
SKP1/
SDN
< 13.2V. While in the test mode,
the regulator performs the normal PFM/PWM operation. SKP1/
SDN
cannot withstand the battery voltage.
Combined Shutdown and Skip-Mode Control Input for BUCK2. Always start BUCK2 before starting BUCK1.
Connect SKP2/
SDN
to V
CC
or drive the pin above 2.8V with external 3.3V-powered CMOS logic for normal
PFM/PWM operation. Connect SKP2/
SDN
to GND or drive the pin below 0.5V to shut down BUCK2. In
shutdown mode, DL2 is forced to V
DD
if the overvoltage protection is enabled. This is done in order to
enforce overvoltage protection even when the regulator is powered down. Leave SKP2/
SDN
floating for the
low-noise forced PWM operation. Low-noise forced-PWM mode causes the inductor current to recirculate
at light loads and suppresses pulse-skipping operation. If OVPSET = V
CC
, then DL2 is forced LOW in
shutdown mode. SKP2/
SDN
cannot withstand the battery voltage.
18
S0
19
S1
20
SKP1/
SDN
21
SKP2/
SDN
22
LIN/
SDN
Linear Regulator Shutdown Control Input. Connect LIN/
SDN
to V
CC
or drive the pin above 2.4V to turn on
the linear regulator. Connect LIN/
SDN
to GND or drive the pin below 0.8V to shut down the linear regulator.
In shutdown mode, LINBSE is forced to a high-impedance state preventing sufficient drive to the external
PNP power transistor in the regulator. LIN/
SDN
cannot withstand the battery voltage.
23
PGOOD
Open-Drain Power-Good Output. PGOOD is forced low during power-up and power-down transitions on
BUCK1. In normal operation, if FBS and OUT2 (FB2) are in regulation, then PGOOD is high. PGOOD is
forced low when SKP1/
SDN
is low. If SKP2/
SDN
is low, OUT2 (FB2) does not affect PGOOD. Normally,
PGOOD is forced high for all VID transitions, and stays high for 4 TIME clock periods after the D/A count is
equalized. If OUT2 is enabled during these conditions and a fault occurs on BUCK2, then PGOOD goes
low. A pullup resistor on PGOOD causes additional finite shutdown current.
24
TON
On-Time Selection Control Input. This four-level input sets the K factor that determines the DH on-time. The
TON times for BUCK2 are shifted to minimize beating between the two regulators. GND = 1000kHz
(BUCK1) and 715kHz (BUCK2), REF = 550kHz (BUCK1) and 390kHz (BUCK2), open = 300kHz (BUCK1)
and 390kHz (BUCK2), V
CC
= 200kHz (BUCK1) and 260kHz (BUCK2).
Pin Description (continued)
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