參數(shù)資料
型號(hào): MAX1714
廠商: Maxim Integrated Products, Inc.
英文描述: High-Speed Step-Down Controller for Notebook Computers
中文描述: 高速、降壓型控制器,用于筆記本電腦
文件頁數(shù): 19/24頁
文件大?。?/td> 443K
代理商: MAX1714
M
High-Speed Step-Down Controller
for Notebook Computers
______________________________________________________________________________________
19
and bulk output capacitance must often be added (see
the V
SAG
equation in
Transient Response
section).
Dropout Design Example: V
IN
= 3V min, V
OUT
= 2V,
f = 300kHz.
The required duty is (V
OUT
+ V
SW
) / (V
IN
-
V
SW
) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The worst-
case on-time is (V
OUT
+ 0.075) / V
IN
·
K = 2.075V / 3V
·
3.35μs-V
·
90% = 2.08μs. The IC duty-factor limitation is:
which meets the required duty.
Remember to include inductor resistance and MOSFET
on-state voltage drops (V
SW
) when doing worst-case
dropout duty-factor calculations.
All-Ceramic-Capacitor Application
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR, are noncombustible, are
relatively small, and are nonpolarized. On the other
hand, they’re expensive and brittle, and their ultra-low
ESR characteristic can result in excessively high ESR
zero frequencies (affecting stability). In addition, their rel-
atively low capacitance value can cause output over-
shoot when going abruptly from full-load to no-load
conditions, unless there are some bulk tantalum or elec-
trolytic capacitors in parallel to absorb the stored energy
in the inductor. In some cases, there may be no room for
electrolytics, creating a need for a DC-DC design that
uses nothing but ceramics.
The all-ceramic-capacitor application of Figure 7
replaces the standard, typical tantalum output capacitors
with ceramics in a 7A circuit. This design relies on hav-
ing a minimum of 5m
parasitic PC board trace resis-
tance in series with the capacitor in order to reduce the
ESR zero frequency. This small amount of resistance is
easily obtained by locating the MAX1714 circuit 2 or 3
inches away from the CPU, and placing all the ceramic
DUTY
t
t
t
2.08 s
+
2.08 s
500ns
80.6%,
ON(MIN)
+
ON(MIN)
OFF(MAX)
=
=
=
V+
V
CC
V
IN
= 7V TO 24V*
SHDN
SKIP
REF
ON/OFF
0.22
μ
F
DL
LX
FB
BST
5
DH
PGND (GND)
AGND (GND)
OUT
( ) ARE FOR THE MAX1714B ONLY.
Q1
+5V
20
1
μ
F
1
μ
F
Q2
0.5
μ
H
0.1
μ
F
C1
1k
R1
C2
CPU
2.5V AT 7A
V
DD
ILIM
MAX1714
R2
C1 = 2 x 10
μ
F/25V TAIYO YUDEN (1812) (TMK432BJ106AM)
C2 = 6 x 47
μ
F/6.3V TAIYO YUDEN (1812) (JMK432BJ476MN)
R1 + R2 = 5m
MINIMUM OF PCB TRACE RESISTANCE (TOTAL)
TON
* FOR HIGHER MINIMUM INPUT VOLTAGE,
*
LESS OUTPUT CAPACITANCE IS ACCEPTABLE.
Figure 7. All-Ceramic-Capacitor Application
Table 5. Approximate K-Factor Errors
TON
SETTING
(kHz)
ERROR (%)
(μs)
APPROXIMATE
K-FACTOR
MIN V
IN
AT V
OUT
= 2V
(V)
200
±10
2.6
300
±10
2.9
450
±12.5
3.2
600
±12.5
3.6
K
FACTOR
5
3.3
2.2
1.7
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