參數(shù)資料
型號: MAX1714
廠商: Maxim Integrated Products, Inc.
英文描述: High-Speed Step-Down Controller for Notebook Computers
中文描述: 高速、降壓型控制器,用于筆記本電腦
文件頁數(shù): 13/24頁
文件大?。?/td> 443K
代理商: MAX1714
M
High-Speed Step-Down Controller
for Notebook Computers
______________________________________________________________________________________
13
multiple-output applications that use a flyback trans-
former or coupled inductor.
Current-Limit Circuit (ILIM)
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that uses the on-state resistance
of the low-side MOSFET as a current-sensing element
(Figure 4). If the current-sense voltage (PGND - LX) is
above the current-limit threshold, the PWM is not allowed
to initiate a new cycle. The actual peak current is greater
than the current-limit threshold by an amount equal to
the inductor ripple current. Therefore, the exact current-
limit characteristic and maximum load capability are a
function of the MOSFET on-resistance, inductor value,
and battery voltage. The reward for this uncertainty is
robust, lossless overcurrent sensing. When combined
with the UVP protection circuit, this current-limit method
is effective in almost every circumstance.
There is also a negative current limit that prevents
excessive reverse inductor currents when V
OUT
is sink-
ing current. The negative current-limit threshold is set to
approximately 120% of the positive current limit, and
therefore tracks the positive current limit when ILIM is
adjusted.
The current-limit threshold is adjusted with an external
resistor-divider at ILIM. A 1μA min divider current is rec-
ommended. The current-limit threshold adjustment
range is from 50mV to 200mV. In the adjustable mode,
the current-limit threshold voltage is precisely 1/10 the
voltage seen at ILIM. The threshold defaults to 100mV
when ILIM is connected to V
CC
. The logic threshold for
switchover to the 100mV default value is approximately
V
CC
- 1V.
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
Design Procedure
).
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the cur-
rent-sense signals seen by LX and PGND. Mount or
place the IC close to the low-side MOSFET with short,
direct traces, making a Kelvin sense connection to the
source and drain terminals.
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving moder-
ate-sized high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook environment, where a large V
BATT
-
V
OUT
differential exists. An adaptive dead-time circuit
monitors the DL output and prevents the high-side FET
from turning on until DL is fully off. There must be a low-
resistance, low-inductance path from the DL driver to the
MOSFET gate for the adaptive dead-time circuit to work
properly; otherwise, the sense circuitry in the MAX1714
will interpret the MOSFET gate as “off” while there is
actually still charge left on the gate. Use very short, wide
traces measuring no more than 20 squares (50 to 100
mils wide if the MOSFET is 1 inch from the MAX1714).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns (typical) internal delay.
The internal pull-down transistor that drives DL low is
robust, with a 0.5
typical on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time of
the inductor node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, you
might still encounter some combinations of high- and
low-side FETs that will cause excessive gate-drain cou-
pling, which can lead to efficiency-killing, EMI-producing
shoot-through currents. This is often remedied by adding
a resistor in series with BST, which increases the turn-on
time of the high-side FET without degrading the turn-off
time (Figure 5).
Figure 3. Pulse-Skipping/Discontinuous Crossover Point
I
I
LOAD
= I
PEAK
/2
ON-TIME
0
TIME
-I
PEAK
L
V
BATT
-V
OUT
i
t
=
Figure 4. ‘‘Valley’’ Current-Limit Threshold Point
I
LIMIT
I
LOAD
0
TIME
-I
PEAK
I
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