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參數(shù)資料
| 型號： | MAX148-MAX149 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs |
| 中文描述： | 2.7V至5.25V，低功耗，8通道，串行10位ADC |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 221K |
| 代理商： | MAX148-MAX149 |
M
+2.7V to +5.25V, Low-Power, 8-Channel,
S erial 10-Bit ADCs
_______________________________________________________________________________________
5
Figure 1
MAX14_ _M
__________________________________________Typic al Operating Charac teristic s
(V
DD
= 3.0V, VREF = 2.500V, f
SCLK
= 2.0MHz, C
LOAD
= 20pF, T
A
= +25°C, unless otherwise noted.)
0
256
512
CODE
768
1024
INTEGRAL NONLINEARITY
vs. CODE
0.10
0.05
-0.10
-0.05
0
M
I
0.125
0
2.25
2.75
4.25
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.100
0.075
0.050
0.025
SUPPLY VOLTAGE (V)
I
3.75
5.25
3.25
4.75
M
MAX149
MAX148
0
0.025
0.050
0.075
0.100
0.125
-60
-20
20
60
100
140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
TEMPERATURE
(°C)
I
M
MAX148
MAX149
V
DD
= 2.7V
TIMING CHARACTERISTICS
(V
DD
= +2.7V to +5.25V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
Note 1:
Tested at V
DD
= 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
MAX149—internal reference, offset nulled; MAX148—external reference (VREF = +2.500V), offset nulled.
Note 4:
Ground “on” channel; sine wave applied to all “off” channels.
Note 5:
Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6:
The common-mode range for the analog inputs is from AGND to V
DD
.
Note 7:
Sample tested to 0.1% AQL.
Note 8:
External load should not change during conversion for specified accuracy.
Note 9:
ADC performance is limited by the converter’s noise floor, typically 300μVp-p.
Note
10:
Guaranteed by design. Not subject to production testing.
Note
11:
The MAX148 typically draws 400μA less than the values shown.
Note
12:
Measured as
|
V
FS
(2.7V) - V
FS
(5.25V)
|
.
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
DIN to SCLK Setup
DIN to SCLK Hold
Figure 1
Figure 2
Figure 1
MAX14_ _C/E
CONDITIONS
ns
20
240
240
Figure 1
ns
ns
t
CSH
t
CH
ns
ns
240
t
STR
t
SCK
CS
Rise to SSTRB Output Disable
SSTRB Rise to SCLK Rise
ns
240
t
SDV
CS
Fall to SSTRB Output Enable
240
t
SSTRB
SCLK Fall to SSTRB
200
t
CL
SCLK Pulse Width Low
ns
200
SCLK Pulse Width High
ns
0
CS
to SCLK Rise Hold
ns
100
t
CSS
CS
to SCLK Rise Setup
ns
240
t
TR
CS
Rise to Output Disable
ns
t
DV
CS
Fall to Output Enable
20
200
t
DO
SCLK Fall to Output Data Valid
ns
0
t
DH
μs
ns
1.5
100
t
ACQ
t
DS
Acquisition Time
0
UNITS
MIN
TYP
MAX
SYMBOL
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