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參數(shù)資料
| 型號： | MAX148-MAX149 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs |
| 中文描述： | 2.7V至5.25V，低功耗，8通道，串行10位ADC |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 221K |
| 代理商： | MAX148-MAX149 |
M
+2.7V to +5.25V, Low-Power, 8-Channel,
S erial 10-Bit ADCs
______________________________________________________________________________________
13
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5μs (
SHDN
= FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9).
CS
does
not need to be held low once a conversion is started.
Pulling
CS
high prevents data from being clocked into
the MAX148/MAX149 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-
impedance state when
CS
goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX148/MAX149 at clock rates exceeding 2.0MHz if
the minimum acquisition time (t
ACQ
) is kept above 1.5μs.
Data Framing
The falling edge of
CS
does
not
start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
SSTRB
CS
SCLK
DIN
DOUT
1
4
8
12
18
20
24
START
SEL2 SEL1 SEL0
BIP
DIF
PD1
PD0
B9
B8
B7
S0
S1
B0
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5
μ
s MAX
(SHDN = FLOAT)
2
3
5
6
7
9
10
11
19
21
22
23
t
CONV
ACQUISITION
1.5
μ
s
(f
SCLK
= 2MHz)
IDLE
A/D STATE
Figure 9. Internal Clock Mode Timing
PD0 CLOCK IN
t
SSTRB
t
CSH
t
CONV
t
SCK
SSTRB
SCLK
DOUT
t
CSS
t
DO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS
Figure 10. Internal Clock Mode SSTRB Detailed Timing
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| MAX149 | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs |
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| MAX149BEPP | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs |
| MAX148ACAP | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs |
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