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參數(shù)資料
| 型號： | MAX148-MAX149 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs |
| 中文描述： | 2.7V至5.25V，低功耗，8通道，串行10位ADC |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 221K |
| 代理商： | MAX148-MAX149 |
M
+2.7V to +5.25V, Low-Power, 8-Channel,
S erial 10-Bit ADCs
12
______________________________________________________________________________________
MAX148/MAX149. The T/H acquires the input signal as
the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 7–10 show the timing characteris-
tics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). SSTRB and DOUT go into a high-impedance
state when
CS
goes high; after the next
CS
falling edge,
SSTRB outputs a logic low. Figure 8 shows the SSTRB
timing in external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120μs.
Internal Clock
In internal clock mode, the MAX148/MAX149 generate
their own conversion clocks internally. This frees the μP
t
SDV
t
SSTRB
PD0 CLOCKED IN
t
STR
SSTRB
SCLK
CS
t
SSTRB
Figure 8. External Clock Mode SSTRB Detailed Timing
CS
SCLK
DIN
DOUT
t
CSH
t
CSS
t
CL
t
DS
t
DH
t
DV
t
CH
t
DO
t
TR
t
CSH
Figure 7. Detailed Serial-Interface Timing
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