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參數(shù)資料
| 型號： | M95320-WDW6TG |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4K X 8 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 0.169 INCH, ROHS COMPLIANT, TSSOP-8 |
| 文件頁數(shù)： | 5/45頁 |
| 文件大?。?/td> | 440K |
| 代理商： | M95320-WDW6TG |
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M95320, M95640, M95320-x, M95640-x
Operating features
4.3
Status Register
Figure 6 shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.
4.4
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write (WRITE) instruction completion
●
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
●
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected.
This is the Hardware Protected Mode (HPM).
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-Protected block size
Status Register Bits
Protected Block
Array Addresses Protected
BP1
BP0
M95640, M95640-W,
M95640-R, M95640-S
M95320, M95320-W,
M95320-R, M95320-S
0
none
0
1
Upper quarter
1800h - 1FFFh
0C00h - 0FFFh
1
0
Upper half
1000h - 1FFFh
0800h - 0FFFh
1
Whole memory
0000h - 1FFFh
0000h - 0FFFh
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95320-WDW6TG/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320-WDW6TG/PC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320WDW6TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit and 64 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320-WDW6TP | 功能描述:電可擦除可編程只讀存儲器 2.5 V to 5.5V 32k RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M95320-WDW6TP/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
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