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參數(shù)資料
| 型號： | M95320-WDW6TG |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 4K X 8 FLASH 2.7V PROM, PDSO8 |
| 封裝： | 0.169 INCH, ROHS COMPLIANT, TSSOP-8 |
| 文件頁數(shù)： | 45/45頁 |
| 文件大?。?/td> | 440K |
| 代理商： | M95320-WDW6TG |
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M95320, M95640, M95320-x, M95640-x
Connecting to the SPI bus
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 3 shows three devices, connected to an MCU, on a SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the
others being high impedance.
Figure 3.
Bus master and memory devices on the SPI bus
1.
The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2.
These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time
(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all
inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become
High at the same time, and so, that the tSHCH requirement is met).
AI12836
SPI Bus Master
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3
CS2
CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
R(2)
VCC
VSS
R(2)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M95320-WDW6TG/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320-WDW6TG/PC | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320WDW6TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit and 64 Kbit serial SPI bus EEPROMs with high-speed clock |
| M95320-WDW6TP | 功能描述:電可擦除可編程只讀存儲器 2.5 V to 5.5V 32k RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| M95320-WDW6TP/P | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Kbit serial SPI bus EEPROMs with high-speed clock |
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