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參數(shù)資料
| 型號(hào)： | M80C186XL |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 10 MHz, MICROPROCESSOR, CPGA68 |
| 封裝： | CERAMIC, PGA-68 |
| 文件頁數(shù)： | 44/44頁 |
| 文件大?。?/td> | 556K |
| 代理商： | M80C186XL |
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M80C186XL
Table 1 M80C186XL Pin Description
(Continued)
Symbol
PGA
Type
Name and Function
Pin No
LCS
UCS and LCS are sampled upon the rising edge of RES If both
pins are held low the M80C186XL will enter ONCE Mode In ONCE
(Continued)
Mode all pins assume a high impedance state and remain so until a
subsequent RESET LCS has a weak internal pullup that is active
only during RESET to ensure that the M80C186XL does not enter
ONCE mode inadvertently
MCS0 PEREQ
38
OI
Mid-Range Memory Chip Select signals are active LOW when a
memory reference is made to the defined mid-range portion of
MCS1 ERROR
37
OI
memory (8K – 512K) These lines do not float during bus HOLD The
MCS2
36
O
address ranges activating MCS0 – 3 are software programmable
MCS3 NPS
35
O
In Enhanced Mode MCS0 becomes a PEREQ input (Processor
Extension Request) When connected to the Math Coprocessor
this input is used to signal the M80C186XL when to make numeric
data transfers to and from the coprocessor MCS3 becomes NPS
(Numeric Processor Select) which may only be activated by
communication to the 80C187 MCS1 becomes ERROR in
Enhanced Mode and is used to signal numerics coprocessor errors
MCS0 PEREQ and MCS1 ERROR have weak internal pullups
which are active during reset
PCS0
25
O
Peripheral Chip Select signals 0 – 4 are active LOW when a
reference is made to the defined peripheral area (64K byte IO or 1
PCS1
27
O
MByte memory space) These lines do not float during bus HOLD
PCS2
28
O
The address ranges activating PCS0 – 4 are software
PCS3
29
O
programmable
PCS4
30
O
PCS5 A1
31
O
Peripheral Chip Select 5 or Latched A1 may be programmed to
provide a sixth peripheral chip select or to provide an internally
latched A1 signal The address range activating PCS5 is software-
programmable PCS5 A1 does not float during bus HOLD When
programmed to provide latched A1 this pin will retain the previously
latched value during HOLD
PCS6 A2
32
O
Peripheral Chip Select 6 or Latched A2 may be programmed to
provide a seventh peripheral chip select or to provide an internally
latched A2 signal The address range activating PCS6 is software-
programmable PCS6 A2 does not float during bus HOLD When
programmed to provide latched A2 this pin will retain the previously
latched value during HOLD
DTR
40
O
Data TransmitReceive controls the direction of data flow through
an external data bus transceiver When LOW data is transferred to
the M80C186XL When HIGH the M80C186XL places write data on
the data bus DTR floats during a bus hold or reset
DEN
39
O
Data Enable is provided as a data bus transceiver output enable
DEN is active LOW during each memory and IO access (including
80C187 access) DEN is HIGH whenever DTR changes state
During RESET DEN is driven HIGH for one clock then floated
DEN also floats during HOLD
NC
Not connected To maintain compatibility with future products do
not connect to these pins
9
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