參數(shù)資料
型號(hào)： M80C186XL
廠商： INTEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, 10 MHz, MICROPROCESSOR, CPGA68
封裝： CERAMIC, PGA-68
文件頁(yè)數(shù)： 43/44頁(yè)
文件大?。?/td> 556K
代理商： M80C186XL
M80C186XL
Table 1 M80C186XL Pin Description
(Continued)
Symbol
PGA
Type
Name and Function
Pin No
LOCK
48
O
LOCK output indicates that other system bus masters are not to gain
control of the system bus LOCK is active LOW The LOCK signal is
requested by the LOCK prefix instruction and is activated at the beginning
of the first data cycle associated with the instruction immediately following
the LOCK prefix It remains active until the completion of that instruction
No instruction prefetching will occur while LOCK is asserted LOCK floats
during bus hold or reset
S0
52
O
Bus cycle status S0 –S2 are encoded to provide bus-transaction
information
S1
53
O
S2
54
O
M80C186XL Bus Cycle Status Information
S2
S1
S0
Bus Cycle Initiated
0
Interrupt Acknowledge
0
1
Read IO
0
1
0
Write IO
0
1
Halt
1
0
Instruction Fetch
1
0
1
Read Data from Memory
1
0
Write Data to Memory
1
Passive (no bus cycle)
The status pins float during HOLD
S2 may be used as a logical MIO indicator and S1 as a DTR indicator
HOLD
50
I
HOLD indicates that another bus master is requesting the local bus The
HOLD input is active HIGH The M80C186XL generates HLDA (HIGH) in
HLDA
51
O
response to a HOLD request Simultaneous with the issuance of HLDA
the M80C186XL will float the local bus and control lines After HOLD is
detected as being LOW the M80C186XL will lower HLDA When the
M80C186XL needs to run another bus cycle it will again drive the local bus
and control lines
In Enhanced Mode HLDA will go low when a DRAM refresh cycle is
pending in the M80C186XL and an external bus master has control of the
bus It will be up to the external master to relinquish the bus by lowering
HOLD so that the M80C186XL may execute the refresh cycle
UCS
34
OI
Upper Memory Chip Select is an active LOW output whenever a memory
reference is made to the defined upper portion (1K – 256K block) of
memory UCS does not float during bus hold The address range activating
UCS is software programmable
UCS and LCS are sampled upon the rising edge of RES If both pins are
held low the M80C186XL will enter ONCE Mode In ONCE Mode all pins
assume a high impedance state and remain so until a subsequent RESET
UCS has a weak internal pullup that is active during RESET to ensure that
the M80C186XL does not enter ONCE Mode inadvertently
LCS
33
OI
Lower Memory Chip Select is active LOW whenever a memory reference is
made to the defined lower portion (1K – 256K) of memory LCS does not
float during bus HOLD The address range activating LCS is software
programmable
8
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