參數(shù)資料
型號(hào)： M80C186XL
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 10 MHz, MICROPROCESSOR, CPGA68
封裝： CERAMIC, PGA-68
文件頁數(shù)： 41/44頁
文件大?。?/td> 556K
代理商： M80C186XL
M80C186XL
Table 1 M80C186XL Pin Description
(Continued)
Symbol
PGA
Type
Name and Function
Pin No
TMR IN 0
20
I
Timer Inputs are used either as clock or control signals
depending upon the programmed timer mode These inputs are
TMR IN 1
21
I
active HIGH (or LOW-to-HIGH transitions are counted) and
internally synchronized Timer Inputs must be tied HIGH when
not being used as clock or retrigger inputs
TMR OUT 0
22
O
Timer outputs are used to provide single pulse or continous
waveform generation depending upon the timer mode selected
TMR OUT 1
23
O
These outputs are not floated during a bus hold
DRQ0
18
I
DMA Request is asserted HIGH by an external device when it is
ready for DMA Channel 0 or 1 to perform a transfer These
DRQ1
19
I
signals are level-triggered and internally synchronized
NMI
46
I
The Non-Maskable Interrupt input causes a Type 2 interrupt An
NMI transition from LOW to HIGH is latched and synchronized
internally and initiates the interrupt at the next instruction
boundary NMI must be asserted for at least one CLKOUT period
The Non-Maskable Interrupt cannot be avoided by programming
INT0
45
I
Maskable Interrupt Requests can be requested by activating one
of these pins When configured as inputs these pins are active
INT1SELECT
44
I
HIGH Interrupt Requests are synchronized internally INT2 and
INT2INTA0
42
IO
INT3 may be configured to provide active-LOW interrupt-
INT3INTA1 IRQ
41
IO
acknowledge output signals All interrupt inputs may be
configured to be either edge- or level-triggered To ensure
recognition all interrupt requests must remain active until the
interrupt is acknowledged When Slave Mode is selected the
function of these pins changes (see Interrupt Controller section
of this data sheet)
A19S6
65
O
Address Bus Outputs (16 – 19) and Bus Cycle Status (3 – 6)
indicate the four most significant address bits during T1 These
A18S5
66
O
signals are active HIGH
A17S4
67
O
A16S3
68
O
During T2 T3 TW and T4 the S6 pin is LOW to indicate a CPU-
initiated bus cycle or HIGH to indicate a DMA-initiated or refresh
bus cycle During the same T-states S3 S4 and S5 are always
LOW These outputs are floated during bus hold or reset
AD15
1
IO
AddressData Bus (0 – 15) signals constitute the time multiplexed
memory or IO address (T1) and data (T2 T3 TW and T4) bus
AD14
3
IO
The bus is active HIGH A0 is analogous to BHE for the lower
AD13
5
IO
byte of the data bus pins D7 through D0 It is LOW during T1
AD12
7
IO
when a byte is to be transferred onto the lower portion of the bus
AD11
10
IO
in memory or IO operations These pins are floated during a bus
AD10
12
IO
hold or reset
AD9
14
IO
AD8
16
IO
AD7
2
IO
AD6
4
IO
AD5
6
IO
AD4
8
IO
AD3
11
IO
AD2
13
IO
AD1
15
IO
AD0
17
IO
6
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