參數(shù)資料
型號： M7A3PE600-FFG256I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA256
封裝： 1 MM PITCH, FBGA-256
文件頁數(shù)： 13/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFG256I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
1-5
In addition, every SRAM block has an embedded FIFO
control unit. The control unit allows the SRAM block to
be configured as a synchronous FIFO without using
additional core VersaTiles. The FIFO width and depth are
programmable. The FIFO also features programmable
Almost-Empty (AEMPTY) and Almost-Full (AFULL) flags in
addition to the normal Empty and Full flags. The
embedded FIFO control unit contains the counters
necessary for the generation of the read and write
address pointers. The embedded SRAM/FIFO blocks can
be cascaded to create larger configurations.
PLL and Clock Conditioning Circuitry (CCC)
ProASIC3E devices provide designers with very flexible
clock conditioning capabilities. Each member of the
ProASIC3E family contains six CCCs, each with an
integrated PLL.
The six CCC blocks are located in the four corners and the
centers of the east and west sides.
To maximize user I/Os, only the center east and west PLLs
are available in devices using the PQ208 package.
However, all six CCC blocks are still usable; the four
corner CCCs allow simple clock delay operations as well
as clock spine access (refer to the "Clock Conditioning
Circuits" section on page 2-13 for more information).
The inputs of the six CCC blocks are accessible from the
FPGA core or from one of several I/O inputs located near
the CCC that have dedicated connections to the CCC
block.
The CCC block has the following key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz to
350 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz to
350 MHz
Clock delay adjustment via programmable and
fixed delays from –7.56 ns to +11.12 ns
Two programmable delay types; refer to Figure 2-16
page 2-31 for more information.
Clock skew minimization
Clock frequency synthesis
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°.
Output phase shift depends on the output divider
configuration.
Output duty cycle = 50% ± 1.5% or better
Low output jitter: worst case < 2.5% × clock period
peak-to-peak period jitter when single global
network used
Maximum acquisition time = 150 s
Low power consumption of 5 mW
Exceptional tolerance to input period jitter –
allowable input jitter is up to 1.5 ns
Four
precise
phases;
maximum
misalignment
between adjacent phases of 40 ps × (350 MHz /
fOUT_CCC)
Global Clocking
ProASIC3E devices have extensive support for multiple
clocking domains. In addition to the CCC and PLL support
described above, there is a comprehensive global clock
distribution network.
Each VersaTile input and output port has access to nine
VersaNets: six chip (main) and three quadrant global
networks (Figure 2-9 on page 2-9). The VersaNets can be
driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to
distribute low-skew clock signals or for rapid distribution
of high-fanout nets.
Pro I/Os with Advanced I/O Standards
The ProASIC3E family of FPGAs features a flexible I/O
structure, supporting a range of voltages (1.5 V, 1.8 V,
2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O
standards,
including
single-ended,
differential,
and
voltage-referenced. For more information, see Table 2-23
The I/Os are organized into banks, with eight banks per
device (two per side). The configuration of these banks
determines the I/O standards supported (see Table 2-14 on
page 2-30 for more information). Each I/O bank is
subdivided into VREF minibanks, which are used by voltage-
referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the
I/Os in a given minibank share a common VREF line.
Therefore, if any I/O in a given VREF minibank is configured
as a VREF pin, the remaining I/Os in that minibank will be
able to use that reference voltage.
Each I/O module contains several input, output, and
enable registers (Figure 2-23 on page 2-33). These
registers allow the implementation of the following:
Single-Data-Rate applications (e.g., PCI 66 MHz,
bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS,
BLVDS,
and
M-LVDS
I/O
for
point-to-point
communications and DDR 200 MHz SRAM using
bidirectional
HSTL
Class
II
–
ProASIC3E banks support M-LVDS with 20 multi-drop
points.
相關(guān)PDF資料
PDF描述
M7A3PE600-FFG484I FPGA, 600000 GATES, PBGA484
M7A3PE600-FFGG256I FPGA, 600000 GATES, PBGA256
M7A3PE600-FFGG484I FPGA, 600000 GATES, PBGA484
M7A3PE600-FPQ208I FPGA, 600000 GATES, PQFP208
M7A3PE600-FPQG208I FPGA, 600000 GATES, PQFP208
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