參數(shù)資料
型號(hào)： M7A3PE600-FFG256I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA256
封裝： 1 MM PITCH, FBGA-256
文件頁數(shù)： 129/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFG256I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-51
Pin Descriptions
Supply Pins
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O
logic.
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O
banks.
Within
the
package,
the
GNDQ
plane
is
decoupled from the simultaneous switching noise
originated from the output buffer ground domain. This
minimizes the noise transfer within the package, and
improves input signal integrity. GNDQ must always be
connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominal 1.5 V. VCC is
also required for powering the JTAG state machine in
addition to VJTAG. Even when a ProASIC3 device is in
bypass mode in a JTAG chain of interconnected devices,
both VCC and VJTAG must remain powered to allow JTAG
signals to pass through the ProASIC3 device.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O
logic. Bx is the I/O bank number. There are eight I/O
banks on ProASIC3E devices plus a dedicated VJTAG bank.
Each bank can have a separate VCCI connection. All I/Os
in a bank will run off the same VCCIBx supply. VCCI can be
1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O
banks should have their corresponding VCCI pins tied to
GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O
bank. X is the bank number. Within the package, the
VMV
plane
is
decoupled
from
the
simultaneous
switching noise originated from the output buffer VCCI
domain. This minimizes the noise transfer within the
package, and improves input signal integrity. Each bank
must have at least one VMV connection and no VMV
should be left unconnected. All I/Os in a bank run off the
same VMVx supply. VMV is used to provide a quiet supply
voltage to the input buffers of each I/O bank. VMVx can
be 1.5 V, 1.8 V, 2.5 V, or 3.3 V nominal voltage. Unused I/O
banks should have their corresponding VMV pins tied to
GND. VMV and VCCI should be at the same voltage within
a given I/O bank. Used VMV pins must be connected to
the corresponding VCCI pins of the same bank (i.e., VMV0
to VCCIB0, VMV1 to VCCIB1, etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominal 1.5 V. There are
six VCCPL pins (PLL power) on ProASIC3E devices. Unused
VCCPL pins should be connected to GND.
VCOMPLA/B/C/D/E/F
PLL Ground
Ground to analog PLL. There are six VCOMPL pins (PLL
ground) on ProASIC3E. Unused VCOMPL pins should be
connected to GND.
VJTAG
JTAG Supply Voltage
ProASIC3E devices have a separate bank for the
dedicated JTAG pins. The JTAG pins can be run at any
voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG
power supply in a separate I/O bank gives greater
flexibility with supply selection and simplifies power
supply and printed circuit board design. If the JTAG
interface is neither used nor planned for use, the VJTAG
pin together with the TRST pin could be tied to GND. It
should be noted that VCC is required to be powered for
JTAG operation; VJTAG alone is insufficient. If a ProASIC3E
device is in a JTAG chain of interconnected boards, the
board containing the ProASIC3E device can be powered
down, provided both VJTAG and VCC to the ProASIC3E
part remain powered; otherwise JTAG signals will not be
able to transition the ProASIC3E device, even in bypass
mode.
VPUMP
Programming Supply Voltage
ProASIC3E
devices
support
single-voltage
ISP
programming of the configuration Flash and FlashROM.
For programming, VPUMP should be 3.3 V nominal.
During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage
between 0 V and 3.6 V.
When the VPUMP pin is tied to ground, it will shut off the
charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
User-Defined Supply Pins
VREF
I/O Voltage Reference
Reference voltage for I/O minibanks. VREF pins are
configured by the user from regular I/Os, and any I/O in a
bank, except JTAG I/Os, which can be designated as the
voltage reference I/O. Only certain I/O standards require
a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II),
SSTL3 (I) and (II), and GTL/GTL+. One VREF pin can support
the number of I/Os available in its minibank.
相關(guān)PDF資料
PDF描述
M7A3PE600-FFG484I FPGA, 600000 GATES, PBGA484
M7A3PE600-FFGG256I FPGA, 600000 GATES, PBGA256
M7A3PE600-FFGG484I FPGA, 600000 GATES, PBGA484
M7A3PE600-FPQ208I FPGA, 600000 GATES, PQFP208
M7A3PE600-FPQG208I FPGA, 600000 GATES, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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