參數(shù)資料
型號(hào): M7A3PE600-FFG256I
元件分類: FPGA
英文描述: FPGA, 600000 GATES, PBGA256
封裝: 1 MM PITCH, FBGA-256
文件頁數(shù): 112/168頁
文件大小: 1335K
代理商: M7A3PE600-FFG256I
ProASIC3E Flash Family FPGAs
2- 36
Advanced v0.5
Hot-Swap Support
Hot-swapping (also called hot plugging) is the operation of hot insertion or hot removal of a card in (or from) a
powered-up system. The levels of hot-swap support and examples of related applications are described in Table 2-17.
The I/Os also need to be configured in hot insertion mode if hot plugging compliance is required.
For ProASIC3E devices requiring level 3 and/or level 4
compliance, the board drivers connected to ProASIC3E I/Os
must have 10 k
(or lower) output drive resistance at hot
insertion, and 1 k
(or lower) output drive resistance at
hot removal. This resistance is the transmitter resistance
sending signal towards the ProASIC3E I/O and no
additional resistance is needed on the board. If that
cannot be assured, three levels of staging can be used to
meet level 3 and/or level 4 compliance. Cards with two
levels of staging should have the following sequence:
Grounds
Powers, I/Os, and other pins
For boards and cards with three levels of staging, card
power supplies must have time to reach their final value
before the I/Os are connected. Pay attention to the sizing
of power supply decoupling capacitors on the card to
ensure that the power supplies are not overloaded with
capacitance.
Cards with three levels of staging should have the
following sequence:
Table 2-17 Levels of Hot-Swap Support
Hot-
Swapping
Level
Description
Power
Applied
to Device Bus State
Card
Ground
Connection
Device
Circuitry
Connected
to Bus Pins
Example of
Application with
Cards that Contain
ProASIC3E Devices
Compliance of
ProASIC3E Devices
1
Cold-swap
No
System
and
card
with
Actel
FPGA
chip
are
powered down and the
card is plugged into the
system. Then the power
supplies are turned on for
the system but not for the
FPGA on the card.
Compliant I/Os can but
do not have to be set to
hot insertion mode.
2
Hot-swap while
reset
Yes
Held in reset
state
Must be made
and
maintained
for 1 msec
before,
during, and
after
insertion/
removal
In
PCI
hot-plug
specification Reset control
circuitry isolates the card
busses
until
the
card
supplies
are
at
their
nominal operating levels
and stable.
Compliant I/Os can but
do not have to be set to
hot-insertion mode.
3
Hot-swap while
bus idle
Yes
Held idle (no
ongoing I/O
processes
during
insertion/
removal)
Same as Level
2
Must remain
glitch-free
during
power-up or
power-down
Board bus shared with
card bus is "frozen," and
there
is
no
toggling
activity on the bus. It is
critical
that
the
logic
states set on the bus
signal
do
not
get
disturbed
during
card
insertion/removal.
Compliant with cards
with
two
levels
of
staging. I/Os have to be
set
to
hot-insertion
mode.
4
Hot-swap on
an active bus
Yes
Bus may have
active I/O
processes
ongoing, but
device being
inserted or
removed
must be idle
Same as Level
2
Same as
Level 3
There is activity on the
system bus, and it is
critical
that
the
logic
states set on the bus
signal
do
not
get
disturbed
during
card
insertion/removal.
: Compliant with cards
with
two
levels
of
staging. I/Os have to be
set
to
hot
insertion
mode.
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