
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17260EJ6V0UD
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(iii) Setting range when CR00n or CR01n is used as a compare register
When CR00n or CR01n is used as a compare register, set it as shown below.
Operation
CR00n Register Setting Range
CR01n Register Setting Range
Operation as interval timer
Operation as square-wave output
Operation as external event counter
0000H < N
≤ FFFFH
0000H
Note
≤ M ≤ FFFFH
Normally, this setting is not used. Mask the
match interrupt signal (INTTM01n).
Operation in the clear & start mode
entered by TI00n pin valid edge input
Operation as free-running timer
0000H
Note
≤ N ≤ FFFFH
0000H
Note
≤ M ≤ FFFFH
Operation as PPG output
M < N
≤ FFFFH
0000H
Note
≤ M < N
Operation as one-shot pulse output
0000H
Note
≤ N ≤ FFFFH (N ≠ M)
0000H
Note
≤ M ≤ FFFFH (M ≠ N)
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output
is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the
timer counter (TM0n register) is changed from 0000H to 0001H.
When the timer counter is cleared due to overflow
When the timer counter is cleared due to TI00n pin valid edge (when clear & start mode is entered by
TI00n pin valid edge input)
When the timer counter is cleared due to compare match (when clear & start mode is entered by match
between TM0n and CR00n (CR00n = other than 0000H, CR01n = 0000H))
Operation enabled
(other than 00)
TM0n register
Timer counter clear
Interrupt signal
is not generated
Interrupt signal
is generated
Timer operation enable bit
(TMC0n3, TMC0n2)
Interrupt request signal
Compare register set value
(0000H)
Operation
disabled (00)
Remarks 1. N: CR00n register set value, M: CR01n register set value
2. For details of TMC0n3 and TMC0n2, see 7.3 (1) 16-bit timer mode control register 0n (TMC0n).
3. n = 0:
PD78F0531, 78F0532, 78F0533
n = 0, 1:
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D