
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
User’s Manual U17260EJ6V0UD
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Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n)
CR00n
(n = 0, 1)
FF13H (CR000), FFB3H (CR001)
FF12H (CR000), FFB2H (CR001)
Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001)
After reset: 0000H
R/W
15
14
13
12
11
10
98
7654
321
0
(i)
When CR00n is used as a compare register
The value set in CR00n is constantly compared with the TM0n count value, and an interrupt request signal
(INTTM00n) is generated if they match. The value is held until CR00n is rewritten.
Caution
CR00n does not perform the capture operation when it is set in the comparison mode, even
if a capture trigger is input to it.
(ii) When CR00n is used as a capture register
The count value of TM0n is captured to CR00n when a capture trigger is input.
As the capture trigger, an edge of a phase reverse to that of the TI00n pin or the valid edge of the TI01n pin
can be selected by using CRC0n or PRM0n.
Figure 7-5. Format of 16-Bit Timer Capture/Compare Register 01n (CR01n)
CR01n
(n = 0, 1)
FF15H (CR010), FFB5H (CR011)
FF14H (CR010), FFB4H (CR011)
After reset: 0000H
R/W
15
14
13
12
11
10
98
7654
321
0
(i)
When CR01n is used as a compare register
The value set in CR01n is constantly compared with the TM0n count value, and an interrupt request signal
(INTTM01n) is generated if they match.
Caution
CR01n does not perform the capture operation when it is set in the comparison mode, even
if a capture trigger is input to it.
(ii) When CR01n is used as a capture register
The count value of TM0n is captured to CR01n when a capture trigger is input.
It is possible to select the valid edge of the TI00n pin as the capture trigger. The TI00n pin valid edge is set
by PRM0n.
Remark
n = 0:
PD78F0531, 78F0532, 78F0533
n = 0, 1:
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D