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7532/7536 Group User’s Manual
Fig. 3.5.11 Structure of USB data toggle synchronization register ......................................3-39
Fig. 3.5.12 Structure of USB interrupt source discrimination register 1 .............................. 3-39
Fig. 3.5.13 Structure of USB interrupt source discrimination register 2 .............................. 3-40
Fig. 3.5.14 Structure of USB interrupt control register...........................................................3-40
Fig. 3.5.15 Structure of USB transmit data byte number set register 0.............................. 3-41
Fig. 3.5.16 Structure of USB transmit data byte number set register 1.............................. 3-41
Fig. 3.5.17 Structure of USB PID control register 0...............................................................3-41
Fig. 3.5.18 Structure of USB PID control register 1...............................................................3-42
Fig. 3.5.19 Structure of USB address register ........................................................................3-42
Fig. 3.5.20 Structure of USB sequence bit initialization register ..........................................3-42
Fig. 3.5.21 Structure of USB control register ..........................................................................3-42
Fig. 3.5.22 Structure of Prescaler 12, Prescaler X.................................................................3-43
Fig. 3.5.23 Structure of Timer 1 ................................................................................................3-43
Fig. 3.5.24 Structure of Timer 2 ................................................................................................3-44
Fig. 3.5.25 Structure of Timer X mode register ......................................................................3-45
Fig. 3.5.26 Structure of Timer X................................................................................................3-46
Fig. 3.5.27 Structure of Timer count source set register .......................................................3-46
Fig. 3.5.28 Structure of Serial I/O2 control register................................................................3-47
Fig. 3.5.29 Structure of Serial I/O2 register.............................................................................3-47
Fig. 3.5.30 Structure of A-D control register............................................................................3-48
Fig. 3.5.31 Structure of A-D conversion register (high-order) ...............................................3-49
Fig. 3.5.32 Structure of A-D conversion register (low-order).................................................3-49
Fig. 3.5.33 Structure of MISRG .................................................................................................3-50
Fig. 3.5.34 Structure of Watchdog timer control register .......................................................3-50
Fig. 3.5.35 Structure of Interrupt edge selection register ......................................................3-51
Fig. 3.5.36 Structure of CPU mode register ............................................................................3-51
Fig. 3.5.37 Structure of Interrupt request register 1 ...............................................................3-52
Fig. 3.5.38 Structure of Interrupt control register 1 ................................................................3-52
Fig. 3.12.1 M37536M4-XXXSP, M37536E8SP pin configuration...........................................3-77
Fig. 3.12.2 M37536RSS pin configuration ................................................................................3-78
Fig. 3.12.3 M37532M4-XXXFP, M37532E8FP pin configuration ...........................................3-79
Fig. 3.12.4 M37532M4-XXXGP pin configuration ....................................................................3-80
Fig. 3.12.5 M37532RSS pin configuration ................................................................................3-81
List of figures