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7532/7536 Group User’s Manual
vii
CHAPTER 3 APPENDIX
Fig. 3.1.1 Power source current measurement circuit in USB mode at oscillation stop ..... 3-5
Fig. 3.1.2 Switching characteristics measurement circuit .........................................................3-6
Fig. 3.1.3 Timing chart ..................................................................................................................3-7
Fig. 3.2.1 I
CC
-V
CC
characteristic example (in double-speed mode) .......................................3-8
Fig. 3.2.2 I
CC
-V
CC
characteristic example (at WIT instruction execution) .............................3-8
Fig. 3.2.3 I
CC
-V
CC
characteristic example (At STP instruction execution, Ta = 25 °C)......3-9
Fig. 3.2.4 I
CC
-V
CC
characteristic example (At STP instruction execution, Ta = 85 °C)......3-9
Fig. 3.2.5 I
CC
-V
CC
characteristic example (at USB suspend, Ta = 25 °C)......................... 3-10
Fig. 3.2.6 I
CC
-V
CC
characteristic example (A-D conversion executed/not executed, f(X
IN
) = 6MHz, in double-speed mode) ... 3-10
Fig. 3.2.7 V
OH
-I
OH
characteristic example of P-channel (Ta = 25 °C): normal port..........3-11
Fig. 3.2.8 V
OH
-I
OH
characteristic example of P-channel (Ta = 85 °C): normal port..........3-11
Fig. 3.2.9 V
OL
-I
OL
characteristic example of N-channel (Ta = 25 °C): Normal port ..........3-12
Fig. 3.2.10 V
OL
-I
OL
characteristic example of N-channel (Ta = 85 °C): Normal port........3-12
Fig. 3.2.11 V
OL
-I
OL
characteristic example of N-channel (Ta = 25 °C): LED drive port... 3-13
Fig. 3.2.12 V
OL
-I
OL
characteristic example N-channel (Ta = 85 °C): LED drive port........3-13
Fig. 3.2.13 I
IL
-V
CC
characteristic example when connecting pull-up transistor...................3-14
Fig. 3.2.14 Definition of A-D conversion accuracy.................................................................. 3-15
Fig. 3.2.15 A-D conversion typical characteristic example ....................................................3-16
Fig. 3.3.1 Sequence of switch the detection edge.................................................................. 3-17
Fig. 3.3.2 Sequence of check of interrupt request bit............................................................3-17
Fig. 3.3.3 Structure of interrupt control register 1 .................................................................. 3-18
Fig. 3.3.4 Sequence of clearing serial I/O ...............................................................................3-18
Fig. 3.3.5 Initialization of processor status register ................................................................3-21
Fig. 3.3.6 Sequence of PLP instruction execution .................................................................. 3-21
Fig. 3.3.7 Stack memory contents after PHP instruction execution .....................................3-21
Fig. 3.3.8 Status flag at decimal calculations ..........................................................................3-22
Fig. 3.3.9 Programming and testing of One Time PROM version ........................................3-23
Fig. 3.3.10 Switching method of CPU mode register .............................................................3-26
Fig. 3.4.1 Selection of packages ...............................................................................................3-27
Fig. 3.4.2 Wiring for the RESET pin .........................................................................................3-27
Fig. 3.4.3 Wiring for clock I/O pins ........................................................................................... 3-28
Fig. 3.4.4 Wiring for CNV
SS
pin ...............................................................................................3-28
Fig. 3.4.5 Wiring for the V
PP
pin of the One Time PROM ....................................................3-29
Fig. 3.4.6 Bypass capacitor across the V
SS
line and the V
CC
line ......................................3-29
Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-30
Fig. 3.4.8 Wiring for a large current signal line ......................................................................3-30
Fig. 3.4.9 Wiring of signal lines where potential levels change frequently ......................... 3-31
Fig. 3.4.10 V
SS
pattern on the underside of an oscillator .....................................................3-31
Fig. 3.4.11 Setup for I/O ports...................................................................................................3-32
Fig. 3.4.12 Watchdog timer by software...................................................................................3-33
Fig. 3.5.1 Structure of Port Pi (i = 0 to 4)...............................................................................3-34
Fig. 3.5.2 Structure of Port Pi direction register (i = 0 to 4) ................................................ 3-34
Fig. 3.5.3 Structure of Pull-up control register ........................................................................3-35
Fig. 3.5.4 Structure of Port P1P3 control register .................................................................. 3-35
Fig. 3.5.5 Structure of Transmit/Receive buffer register ........................................................3-36
Fig. 3.5.6 Structure of UART status register ........................................................................... 3-36
Fig. 3.5.7 Structure of USB status register..............................................................................3-37
Fig. 3.5.8 Structure of Serial I/O1 control register.................................................................. 3-38
Fig. 3.5.9 Structure of UART control register ..........................................................................3-38
Fig. 3.5.10 Structure of Baud rate generator........................................................................... 3-39
List of figures