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參數(shù)資料
| 型號： | M5M5T5636UG-22 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（524288 - Word的36位）網(wǎng)絡的SRAM |
| 文件頁數(shù)： | 16/23頁 |
| 文件大小： | 287K |
| 代理商： | M5M5T5636UG-22 |
MITSUBISHI LSIs
M5M5T5636UG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
16
MITSUBISHI
ELECTRIC
Advanced Information
M5M5T5636UG REV.0.1
Bypass Register
The Bypass resister is a single-bit register that can be placed between the TDI and TDO pins. It allows serial test data to be passed
through the SRAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the SRAM's input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pins. The relationship
between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the SRAM's I/O ring when the controller is in the
Capture-RD state and then is placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instruction can be used to activate the Boundary Scan Register.
Identification (ID) Register
The ID register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the Capture-DR
state with the IDCODE Instruction loaded in the Instruction Register. The code is loaded from 32-bit on-chip ROM. It describes various
attributes of the SRAM (see page 20). The register is then placed between the TDI and TDO pins when the controller is moved into
Shift-DR state. Bit 0 in the register is the LSB and the first to reach the TDO pin when shifting begins.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific (Private)
instructions. Some public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in
prescribed ways. The TAP Controller in this device is not fully 1194.1-compliant because some of the mandatory 1149.1 instructions are
not fully implemented. The TAP on this device may be used to monitor all input and I/O pads. This device will not perform INTEST or
PRELOAD portion of the SAMPLE/PRELOAD command.
When the TAP controller is placed in the Shift-IR state, the Instruction Register is placed between the TDI and TDO pins. In this state the
desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at the TDO output). For all
instructions, the TAP executes newly loaded instructions only when the controller is moved to the Update-IR state. The TAP Instruction
Set for this device is listed in the following table.
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between the TDI and TDO pins. This
occurs when the TAP Controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the
Instruction Register, moving the TAP Controller into the Capture-DR state loads the data in the SRAM's input and I/O buffers into the
Boundary Scan Register. Because the SRAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results cannot be expected. SRAM input signals must be stabilized for long
enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH). The SRAM's clock inputs need not be paused for any
other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to the Shift-DR state
then places the Boundary Scan Register between the TDI and TDO pins. Because the PRELOAD portion of the command is not
implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the
Instruction Register has the same effect as the Pause-DR command. This functionality is not Standard 1149.1 compliant.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5T5636UG-25 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:MITSUBISHI LSIs 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| M5M5T5672TG | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
| M5M5T5672TG-20 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
| M5M5T5672TG-22 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
| M5M5T5672TG-25 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM |
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