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參數(shù)資料
| 型號： | M5M4V4405CTP-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| 中文描述： | 江戶（超頁模式）4194304位（1048576 - Word的4位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 4/27頁 |
| 文件大?。?/td> | 293K |
| 代理商： | M5M4V4405CTP-6 |
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EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
M5M4V4405CJ,TP-6,-7,-6S,-7S
MITSUBISHI LSIs
Test conditions
4
SWITCHING CHARACTERISTICS
(Ta=0~70C, V
CC
=3.3V±0.3V, Vss
=
0V, unless otherwise noted, see notes 6,14,15)
ns
ns
ns
ns
ns
ns
15
60
30
33
15
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
M5M4V4405C-6,-6S
Min
M5M4V4405C-7,-7S
Min
20
70
35
38
20
Parameter
Symbol
Limits
@
Unit
Max
Max
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
OHC
t
OHR
Note 6: An initial pause of 200μs is required after power-up followed by a minimum of eight initialization cycles (RAS only refresh or CAS before RAS refresh
cycles)
@@@@@@@@@@@@@
@
Note the RAS may be cycled during the initial pause. And eight initialization cycles are required after prolonged periods (greater than
t
REF(max)
) of
RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 100pF, V
OH
=2.4V(I
OH
=-2mA) and V
OL
=0.4V(I
OL
=2mA).
The reference levels for measuring of output signals are 2.0V(V
OH
) and 0.8V(V
OL
).
8: Assumes that
t
RCD
≥
t
RCD(max)
and
t
ASC
≥
t
ASC(max)
and
t
CP
≥
t
CP(max)
.
9: Assumes that
t
RCD
≤
t
RCD(max)
and
t
RAD
≤
t
RAD(max)
. If
t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will
increase by amount that
t
RCD
exceeds the value shown.
10: Assumes that
t
RAD
≥
t
RAD(max)
and
t
ASC
≤
t
ASC(max)
.
11: Assumes that
t
CP
≤
t
CP(max)
and
t
ASC
≥
t
ASC(max)
.
12:
t
OEZ (max)
,
t
WEZ(max)
,
t
OFF(max)
and
t
REZ(max)
defines the time at which the output achieves the high impedance state(
I
OUT
≤
|
±10μA
|)
and is
not reference to V
OH(min)
or V
OL(max)
.
13: Output is disabled after both RAS and CAS go to high.
CAPACITANCE
Limits
Typ
Min
Max
5
7
7
Unit
pF
pF
pF
C
I (A)
C
I (CLK)
C
I / O
Symbol
Parameter
V
I
=V
SS
f=1MHz
V
I
=25mVrms
(Ta=0~70C, V
CC
=3.3V±0.3V, Vss
=
0V, unless otherwise noted)
t
CLZ
t
OEZ
t
WEZ
t
OFF
t
REZ
(Note 12)
(Note 12)
(Note 12,13)
(Note 12,13)
(Note 7)
5
15
15
ns
ns
ns
ns
ns
15
15
5
20
20
20
20
5
ns
5
5
5
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
Output disable time after OE high
Output disable time after WE low
Output disable time after CAS high
Output disable time after RAS high
Output low impedance time from CAS low
(Note 13)
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| M5M4V4405CTP-6S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
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