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參數(shù)資料
| 型號： | M5M4V4405CTP-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| 中文描述： | 江戶（超頁模式）4194304位（1048576 - Word的4位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 25/27頁 |
| 文件大?。?/td> | 293K |
| 代理商： | M5M4V4405CTP-6 |
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EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
M5M4V4405CJ,TP-6,-7,-6S,-7S
MITSUBISHI LSIs
Test Mode Set Cycle
(Note 34)
The cycle is also avaiilable for initialization cycle, but in this case device enters test mode.
The test mode function is initiated with a W and CAS before RAS cycle(WCBR cycle) as specified above timing diagram.
The test mode function is terminated by either a CAS before RAS(CBR) refresh or a RAS only refresh cycle.
During the test mode, the device is internally organized as 4-bits wide (256 kilobytes deep) for each DQ (input / output) port.
No addressing of A
0
, A
1
(column only) is required.
During a write cycle, data on the each DQ (input) pin is written in parallel into all 4-bits for each DQ port and can be written
independently for each DQ port.
During a read cycle, the each DQ (output) pin indicates independently a HIGH state if all 4-bits are equal, and a LOW state
if any bits differ.
During the test mode operation, a WCBR cycle is used to perform refresh.
Note 34
:
CAS
W
DQ
1
~DQ
4
(INPUTS)
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
RAS
t
RC
t
ASR
t
CRP
t
RPC
t
RP
COLUMN
ADDRESS
DQ
1
~DQ
4
(OUTPUTS)
ROW
ADDRESS
t
RPC
t
CSR
t
CHR
t
CPN
t
RCH
t
RCS
t
OFF
Hi-Z
OE
V
IH
V
IL
t
OEZ
t
RP
A
0
~A
9
t
WSR
t
WHR
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| M5M4V4405CTP-6S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
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