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參數(shù)資料
| 型號： | M5M4V4405CTP-6S |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| 中文描述： | 江戶（超頁模式）4194304位（1048576 - Word的4位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 293K |
| 代理商： | M5M4V4405CTP-6S |
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EDEDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
MITMITSUBISHI LSIs
PIN CONFIGURATION (TOP VIEW)
time
(min.ns)
110
Cycle
tion
(typ.mW)
264
DQ
1
Outline 26P3Z-E (300mil TSOP)
DQ
2
A
0
A
1
A
2
W
RAS
A
3
V
CC
A
9
2
3
4
5
13
12
11
10
9
V
SS
DQ
4
DQ
3
CAS
OE
A
4
A
7
A
6
A
5
16
15
26
25
24
23
17
18
22
14
A
8
Standard 26 pin SOJ, 26 pin TSOP(II)
Single 3.3V±0.3V supply
Low stand-by power dissipation
CMOS lnput level .................................................1.8mW(Max)*
CMOS lnput level ................................................180μW(Max)
Low operating power dissipation
M5M4V4405Cxx-6, -6S .....................................288.0mW (Max)
M5M4V4405Cxx-7, -7S ....................................252.0mW (Max)
Self refresh capabiility
*
Self refresh current ..............................................100μA(max)
Extended refresh capability
*
Extended refresh current ....................................100μA(max)
Hyper-page mode (1024-bit random access), Read-modify- write,
RAS-only refresh CAS before RAS refresh, Hidden refresh, CBR
self refresh(-6S,-7S) capabilities.
Early-write mode and OE and W to control output buffer impedance
1024 refresh cycles every 16.4ms (A
0
~A
9
)
1024refresh cycle every128ms (A
0
~A
9
)
*
*: Applicable to self refresh version (M5M4V4405Cxx-6S,-7S:
option) only
This is a family of 1048576-word by 4-bit dynamic RAMS,
fabricated with the high performance CMOS process,and is ideal
for large-capacity memory systems where high speed, low power
dissipation , and low costs are essential.
The use of quadruple-layer polysilicon process combined with
silicide technology and a single-transistor dynamic storage stacked
capacitor cell provide high circuit density at reduced costs.
Multiplexed address inputs permit both a reduction in pins and an
increase in system densities.
Self or extended refresh current is low enough for battery
back-up application.
1
DESCRIPTION
FEATURES
Type name
RAS
access
time
(max.ns)
CAS
access
time
(max.ns)
Address
access
time
(max.ns)
M5M4V4405CXX-7, -7S
70
20
35
130
231
20
OE
M5M4V4405CXX-6, -6S
60
15
30
15
PIN DESCRIPTION
Pin name
A
0
~A
9
DQ
1
~DQ
4
RAS
CAS
W
OE
V
CC
V
SS
Function
M5M4V4405CJ,TP-6,-7,-6S,-7S
DQ
1
Outline 26P0J (300mil SOJ)
DQ
2
A
0
A
1
A
2
W
RAS
A
3
V
CC
A
9
1
2
3
4
5
13
12
11
10
9
V
SS
DQ
4
DQ
3
CAS
OE
A
4
A
7
A
6
A
5
16
15
26
25
24
23
17
18
22
14
A
8
XX=J, TP
APPLICATION
Lap top personal computer,Solid state disc, Microcomputer
memory, Refresh memory for CRT
access
time
(max.ns)
Address inputs
Data inputs / outputs
Row address strobe input
Column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M4V4405CTP-7 | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| M5M4V4405CTP-7S | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| M5M5256DRV-12VXL-I | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DRV-12VLL | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| M5M5256DRV-12VLL-I | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V4405CTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| M5M4V4405CTP-7S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
| M5M4V4S40CTP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| M5M4V4S40CTP-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:4M (2-BANK x 131072-WORD x 16-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
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