參數(shù)資料
型號： M37905M6C-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： DIO, BAT54C, DUAL SHOTTKEY, COMMON CATHODE, SOT23
中文描述： 16位CMOS微機
文件頁數(shù)： 85/102頁
文件大小： 881K
代理商： M37905M6C-XXXSP
85
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 96 Bit configuration of particular function select register 1
Fig. 97 Bit configuration of watchdog timer frequency select register
7
6
5
4
3
2
1
0
Watchdog timer frequency select register
Watchdog timer frequency select bit
0 : Select Wf
512
1 : Select Wf
32
Watchdog timer clock source select bits at STP termination
0 0 : fX
32
0 1 : fX
16
1 0 : fX
128
1 1 : fX
64
Address
61
16
When the external clock input select bit (bit 1 of the particular func-
tion select register 0) =
“
0
”
or the system clock select bit (bit 5 of the
clock control register 0) =
“
1
”
, the watchdog timer will start counting
down with one of the above divide clocks, fX
16
to fX
128
, after the os-
cillation circuit and PLL circuit have been restarted their operations
owing to an interrupt. The most significant bit of the watchdog timer
reaching
“
0
”
, supply of
φ
BIU
and
φ
CPU
restarts.
On the other hand, when the external clock input select bit =
“
1
”
and
the system clock select bit =
“
0
”
, supply of
φ
BIU
and
φ
CPU
will restart
immediately after the oscillation circuit and PLL circuit have been re-
started their operations owing to an interrupt. (In actual fact, after the
selected one of the above divide clocks, fX
16
to fX
128
, has been
changed from
“
H
”
to
“
L
”
, this supply will restart.)
7
6
5
4
0
3
2
0
1
0
Particular function select register 1
STP-instruction-execution status bit
(Note 1)
0: Normal operation.
1: STP instruction is under execution.
WIT-instruction-execution status bit
(Note 1)
0: Normal operation.
1: WIT instruction is under execution.
Fix this bit to
“
0
”
.
System clock stop select bit at WIT
(Note 2)
0: In wait mode, system clock f
sys
is active.
1: In wait mode, system clock f
sys
is inactive.
Fix this bit to
“
0
”
.
Timer B2 clock source select bit
Valid in event counter mode:
0: Clock input from pin TB2
IN
is counted.
1: fX
32
(f(X
IN
)/32) is counted.
Address
63
16
Notes 1:
At power-on reset, this bit becomes
“
0
”
. At hardware reset or software reset, this bit
retains the value just before reset. Even when
“
1
”
is try to be written, the bit status will
not change.
2:
Setting this bit to
“
1
”
must be performed just before execution of the WIT instruction.
Also, after the wait state is terminated, this bit must be cleared to
“
0
”
immediately.
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