參數(shù)資料
型號(hào)： M37905M6C-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： DIO, BAT54C, DUAL SHOTTKEY, COMMON CATHODE, SOT23
中文描述： 16位CMOS微機(jī)
文件頁(yè)數(shù)： 73/102頁(yè)
文件大?。?/td> 881K
代理商： M37905M6C-XXXSP
73
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
1/16
Watchdog timer
frequency select bit
“FFF
16
” is set.
Writing to watchdog
timer register
STP
instruction
Watchdog timer
interrupt request
Wf
32
Wf
512
Watchdog timer
f
2
Wait mode
1/16
1
0
Watchdog timer register: address 60
16
Watchdog timer frequency select register: bit 0 at address 61
16
Watchdog timer clock source select bits at STP state termination: bits 6, 7 at address 61
16
When the most significant bit of the watchdog timer becomes “0”, this signal will be generated.
Note:
During the stop mode and until the stop mode is terminated, setting for disabling the
watchdog timer is ignored.
RESET
Disables watchdog
timer
(Note)
.
fX
16
fX
32
fX
64
fX
128
Watchdog timer clock source select
bits at STP state termination
Stop mode
Divided f(X
IN
)
WATCHDOG TIMER
The watchdog timer is used to detect unexpected execution se-
quence caused by software runaway and others. Figure 83 shows
the block diagram of the watchdog timer.
The watchdog timer consists of a 12-bit binary counter.
The watchdog timer counts clock Wf
32
, which is obtained by dividing
the peripheral devices
’
clock f
2
by 16; or clock Wf
512
, which is ob-
tained by doing it by 256. Bit 0 of the watchdog timer frequency se-
lect register (watchdog timer frequency select bit) shown in Figure 84
selects which clock is to be counted.
Wf
512
is selected when this bit 0 is
“
0
”
, and Wf
32
is selected when bit
0 is
“
1
”
. Bit 0 is cleared to
“
0
”
after reset.
FFF
16
is set in the watchdog timer when
“
L
”
level voltage is applied
to pin RESET, STP instruction is executed, data is written to the
watchdog timer register (address 60
16
), or the most significant bit of
the watchdog timer becomes
“
0
”
.
After FFF
16
is set in the watchdog timer, when the watchdog timer
counts Wf
32
or Wf
512
by 2048 counts, the most significant bit of the
watchdog timer becomes
“
0
”
, the watchdog timer interrupt request
bit is set to
“
1
”
, and FFF
16
is set again in the watchdog timer.
In program coding, make sure that data is written in the watchdog
timer before the most significant bit of the watchdog timer becomes
“
0
”
. If this routine is not executed owing to unexpected program ex-
ecution or others, the most significant bit of the watchdog timer be-
Fig. 83 Block diagram of watchdog timer
Fig. 84 Bit configuration of watchdog timer frequency select register
7
6
5
4
3
2
1
0
Watchdog timer frequency select register
Watchdog timer frequency select bit
0 : Wf
512
1 : Wf
32
Watchdog timer clock source select bits at STP
state termination
0 0 : fX
32
0 1 : fX
16
1 0 : fX
128
1 1 : fX
64
Address
61
16
comes
“
0
”
and an interrupt is generated.
The microcomputer can generate a reset pulse by writing
“
1
”
to bit 6
(software reset bit) of processor mode register 0 in an interrupt rou-
tine and can be restarted.
The watchdog timer can also be used to return from the
STP
state,
where a clock has stopped its operation owing to the
STP
instruction
execution. For details, refer to the sections on the clock generating
circuit and standby function.
The watchdog timer stops its operation in the following cases, and at
this time, input to the watchdog timer is disabled:
When the external area is accessed in the hold state
In the wait mode
In the stop mode
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