
23
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Interrupts caused by the address matching detection and when di-
viding by zero are software interrupts and are not included in Figure
14.
Other interrupts previously mentioned are A-D converter, UART, etc.
interrupts. The priority of these interrupts can be changed by chang-
ing the priority level in the corresponding interrupt control register by
software.
Figure 15 shows a diagram of the interrupt priority detection circuit.
When an interrupt is caused, each interrupt device compares its own
priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the pri-
orities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is
“
0
”
. The request is not accepted if flag I is
“
1
”
. The reset and
watchdog timer interrupts are not affected by the interrupt disable
flag I.
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag I is
set to
“
1
”
.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to
“
0
”
and the processor interrupt priority level (IPL) in the
Table 4. Addresses of interrupt control registers
Interrupt control registers
INT
3
interrupt control register
INT
4
interrupt control register
A-D interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
INT
1
interrupt control register
INT
2
interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
Timer A5 interrupt control register
Timer A6 interrupt control register
Timer A7 receive control register
Timer A8 interrupt control register
Timer A9 interrupt control register
INT
5
interrupt control register
INT
6
interrupt control register
INT
7
interrupt control register
Addresses
00006E
16
00006F
16
000070
16
000071
16
000072
16
000073
16
000074
16
000075
16
000076
16
000077
16
000078
16
000079
16
00007A
16
00007B
16
00007C
16
00007D
16
00007E
16
00007F
16
0000F1
16
0000F2
16
0000F5
16
0000F6
16
0000F7
16
0000F8
16
0000F9
16
0000FD
16
0000FE
16
0000FF
16
Fig. 14 Interrupt priority
Fig. 15 Interrupt priority detection
Watchdog
timer
Reset
Priority is determined by hardware
A-D converter, UART, etc. interrupts
Priority can be changed by software inside
.
INT
2
INT
1
INT
0
Reset
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
Watchdog timer
I P L
Interrupt request
Level 0
Interrupt disable flag I
INT
3
INT
7
INT
6
INT
5
INT
4
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
UART2 transmit
UART2 receive