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69
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Operation mode
The operation mode is selected by bits 3 and 4 of A-D control regis-
ter 0 and bit 2 of A-D control register 1. The available operation
modes are one-shot, repeat, single sweep, repeat sweep 0, and re-
peat sweap 1. Note that, as for pins AN
8
through AN
11
, only one-shot
and repeat modes can be selected. Either an A-D converter or a
comparator can be selected respectively for each pin in the following
5 modes. The following description applies to the case where the bit
of the comparator function select register 0/1 is
“
0
”
and an A-D con-
verter is selected. It also applies to a comparator
’
s operation except
that an A-D conversion is changed to a comparator operation and
the result of the comparison is stored into the comparator result reg-
ister 0/1.
(1) One-shot mode
One-shot mode is selected when bits 3 and 4 of A-D control register
0 are
“
0
”
. The A-D conversion pins are selected with bits 0 to 2 of
A-D control register 0 and bits 0 to 3 of A-D control register 2. A-D
conversion or comparator operation is started when bit 6 of A-D con-
trol register 0 (A-D conversion start bit) is set to
“
1
”
.
When the ANi (i = 11 through 0) comparator function select bit of the
comparator function select register 0/1 =
“
0
”
and bit 3 of the A-D con-
trol register 1 =
“
1
”
, A-D conversion ends 59
φ
AD
cycles after, and the
interrupt request bit of the A-D conversion interrupt control register is
set to
“
1
”
. At the same time, bit 6 of the A-D control register 0 (A-D
conversion start bit) is cleared to
“
0
”
and this A-D conversion stops.
The result of A-D conversion is stored into the A-D register corre-
sponding to the selected pin.
When the ANi (i = 11 through 0) comparator function select bit of the
comparator function select register 0/1 =
“
1
”
, a comparator operation
ends 14
φ
AD
cycles after, and the interrupt request bit of the A-D con-
version interrupt control register is set to
“
1
”
. At the same time, bit 6
of the A-D control register 0 (A-D conversion start bit) is cleared to
“
0
”
and the comparator operation stops. The result of the compari-
son is stored into the bits of the comparator result register corre-
sponding to the selected pin.
Fig. 78 Bit configuration of A-D control register 0
A-D control register 0
Address
1E
16
7
6
5
0
4
3
2
1
0
Analog input select bits
(Note 1)
(Valid in the one-shot mode and repeat mode.)
0 0 0 : AN
0
0 0 1 : AN
1
0 1 0 : AN
2
0 1 1 : AN
3
1 0 0 : AN
4
1 0 1 : AN
5
1 1 0 : AN
6
1 1 1 : AN
7
(Note 2)
A-D operation mode select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or Repeat sweep mode 1
Fix this bit to
“
0
”
.
A-D conversion start bit
(Note 3)
0 : A-D conversion stopped.
1 : A-D conversion started.
A-D conversion frequency (
φ
AD
) select bit 0
Notes 1:
Invalid in the single sweep mode and repeat sweep mode 0. (Each of these bits may be
“
0
”
or
“
1
”
.)
2:
When using pin AN
7
, make sure that the D-A
0
output enable bit (bit 0 at address 96
16
) =
“
0
”
(output disabled).
3:
Use the
MOVM (MOVMB)
or
STA (STAB or STAD)
instruction for rewriting to this bit.
4:
Rewriting to each bit of the A-D control register 0 (except for bit 6) must be performed while A-D conversion is stopped.