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29
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
(2) Event counter mode [01]
Figure 23 shows the bit configuration of the timer Ai mode register in
the event counter mode. In event counter mode, bit 0 of the timer Ai
mode register must be
“
1
”
and bits 1 and 5 must be
“
0
”
.
The input signal from the TAi
IN
pin is counted when the count start
bit shown in Figure 21 is
“
1
”
and counting is stopped when it is
“
0
”
.
Count is performed at the fall of the input signal when bit 3 is
“
0
”
and
at the rise of the signal when it is
“
1
”
.
In event counter mode, whether to increment or decrement the count
can be selected with the up-down bit or the input signal from the
TAi
OUT
pin.
When bit 4 of the timer Ai mode register is
“
0
”
, the up-down bit is
used to determine whether to increment or decrement the count
(decrement when the bit is
“
0
”
and increment when it is
“
1
”
). Figure
24 shows the bit configuration of the up-down register.
When bit 4 of the timer Ai mode register is
“
1
”
, the input signal from
the TAi
OUT
pin is used to determine whether to increment or decre-
ment the count. However, note that bit 2 must be
“
0
”
if bit 4 is
“
1
”
. It is
because if bit 2 is
“
1
”
, TAi
OUT
pin becomes an output pin to output
pulses.
The count is decremented when the input signal from the TAi
OUT
pin
is
“
L
”
and incremented when it is
“
H
”
. Determine the level of the input
signal from the TAi
OUT
pin before a valid edge is input to the TAi
IN
pin.
An interrupt request signal is generated and the interrupt request bit
in the timer Ai interrupt control register is set when the counter
reaches 0000
16
(decrement count) or FFFF
16
(increment count). At
the same time, the contents of the reload register is transferred to the
counter and the count is continued.
When bit 2 is
“
1
”
, each time the counter reaches 0000
16
(decrement
Fig. 23 Bit configuration of timer Ai mode register in event counter mode
7
×
6
×
5
0
4
3
2
1
0
0
1
0 1 : Always
“
01
”
in event counter mode
0 : No pulse output
1 : Pulse output
0 : Count at the falling edge of input signal
1 : Count at the rising edge of input signal
0 : Increment or decrement according to up/down bit
1 : Increment or decrement according to TAi
OUT
pin input signal level
0 : Always
“
0
”
in event counter mode
× ×
: Not used in event counter mode
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Addresses
56
16
57
16
58
16
59
16
5A
16
Timer A5 mode register
Timer A6 mode register
Timer A7 mode register
Timer A8 mode register
Timer A9 mode register
Addresses
D6
16
D7
16
D8
16
D9
16
DA
16
count) or FFFF
16
(increment count), the waveform
’
s polarity is re-
versed and is output from TAi
OUT
pin.
If bit 2 is
“
0
”
, TAi
OUT
pin can be used as a normal port pin.
However, if bit 4 is
“
1
”
and the TAi
OUT
pin is used as an output pin,
the output from the pin changes the count direction. Therefore, bit 4
must be
“
0
”
unless the output from the TAi
OUT
pin is to be used to se-
lect the count direction.
Data write and data read are performed in the same way as for timer
mode. That is, when data is written to timer Ai halted, it is also writ-
ten to the reload register and the counter. When data is written to
timer Ai which is busy, the data is written to the reload register, but
not to the counter. The counter is reloaded with new data from the
reload register at the next reload time. The counter can be read at
any time.
In event counter mode, whether to increment or decrement the
counter can also be determined by supplying two kinds of pulses of
which phases differ by 90
°
to timer A2, A3, A4, A7, A8 or A9. There
are two types of two-phase pulse processing operations. One uses
timers A2, A3, A7, and A8 and the other uses timers A4 and A9. In
both processing operations, two pulses described above are input to
the TA
jOUT
(j = 2 to 4, 7 to 9) pin and TAj
IN
pin respectively.
When timers A2, A3, A7, and A8 are used, as shown in Figure 25, the
count is incremented when a rising edge is input to the TAk
IN
(k=2,
3, 7, 8) pin after the level of TAk
OUT
pin changes from
“
L
”
to
“
H
”
, and
when the falling edge is input, the count is decremented.
For timers A4 and A9, as shown in Figure 26, when a phase-related
pulse with a rising edge input to the TAl
IN
(l = 4, 9) pin is input after
the level of TAl
OUT
pin changes from
“
L
”
to
“
H
”
, the count is
incremented at the respective rising edge and falling edge of the
TAl
OUT
pin and TAl
IN
pin.