參數(shù)資料
型號(hào)： M37905M4C-XXXSP
廠商： Mitsubishi Electric Corporation
英文描述： 16 BIT CMOS MICROCOMPUTER
中文描述： 16位CMOS微機(jī)
文件頁(yè)數(shù)： 24/102頁(yè)
文件大小： 881K
代理商： M37905M4C-XXXSP
24
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting the
interrupt disable flag I to
“
0
”
and enable further interrupts.
For reset, watchdog timer, zero divide, and address match detection
interrupts, which do not have an interrupt control register, the proces-
sor interrupt level (IPL) is set as shown in Table 5.
The interrupt request bit and the interrupt priority level of each inter-
rupt source are sampled and latched at each operation code fetch
cycle while f
sys
is
“
H
”
. However, no sampling pulse is generated until
the cycles whose number is selected by software has passed, even
if the next operation code fetch cycle is generated. The detection of
an interrupt which has the highest priority is performed during that
time.
As shown in Figure 16, there are three different interrupt priority de-
tection time from which one is selected by software. After the se-
lected time has elapsed, the highest priority is determined and is
processed after the currently executing instruction has been com-
pleted.
The time is selected with bits 4 and 5 of the processor mode register
0 (address 5E
16
) shown in Figure 11. Table 6 shows the relationship
between these bits and the number of cycles. After a reset, the pro-
cessor mode register 0 is initialized to
“
00
16.
”
Therefore, the longest
time is automatically set, however, the shortest time must be se-
lected by software.
Table 5.
Value loaded in processor interrupt level (IPL) during an interrupt
Interrupt types
Reset
Watchdog timer
Zero divide
Address matching detection
Setting value
0
7
Not change value of IPL.
Not change value of IPL.
Table 6. Relationship between interrupt priority detection time select
bit and number of cycles
Priority detection time select bit
Bit 5
0
0
1
0
Note:
For system clock f
sys
, refer to the section on the clock gener-
ating circuit.
Bit 4
0
1
7 cycles of f
sys
4 cycles of f
sys
2 cycles of f
sys
Number of cycles
(Note)
Fig. 16 Interrupt priority detection time
Operation code fetch cycle
f
sys
Sampling pulse
Priority detection time
Select one between 00 to
10 with bits 4 and 5 of
processor mode register 0
0 0
0 1
1 0
b5 b4
(Note)
Note:
This pulse resides when 2 cycles of f
sys
is selected.
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